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PI7C7100 Datasheet(PDF) 49 Page - Pericom Semiconductor Corporation |
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PI7C7100 Datasheet(HTML) 49 Page - Pericom Semiconductor Corporation |
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49 / 132 page ![]() 41 09/18/00 Rev 1.1 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567 PI7C7100 3-Port PCI Bridge ADVANCE INFORMATION a t a d y r a d n o c e S t i b d e t c e t e d y t i r a p n o i t c a s n a r T e p y T n o i t c e r i D s a w r o r r e e r e h w s u B d e t c e t e d y r a d n o c e S / y r a m i r P s t i b e s n o p s e r r o r r e y t i r a p 0d a e Rm a e r t s n w o Dy r a m i r Px / x 1 1d a e Rm a e r t s n w o Dy r a d n o c e S1 / x 0d a e Rm a e r t s p Uy r a m i r Px / x 0d a e Rm a e r t s p Uy r a d n o c e Sx / x 0e t i r w d e t s o Pm a e r t s n w o Dy r a m i r Px / x 1e t i r w d e t s o Pm a e r t s n w o Dy r a d n o c e S1 / x 0e t i r w d e t s o Pm a e r t s p Uy r a m i r Px / x 0e t i r w d e t s o Pm a e r t s p Uy r a d n o c e Sx / x 0e t i r w d e y a l e Dm a e r t s n w o Dy r a m i r Px / x 1e t i r w d e y a l e Dm a e r t s n w o Dy r a d n o c e S1 / x 0e t i r w d e y a l e Dm a e r t s p Uy r a m i r Px / x 0e t i r w d e y a l e Dm a e r t s p Uy r a d n o c e Sx / x 1x =don’t care Table 7–4. Setting Secondary Interface Data Parity Detected Bit Table 7–4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions: • The PI7C7100 must be a master on the secondary bus. • The parity error response bit must be set in the bridge control register of secondary interface. • The S_PERR# signal is detected asserted or a parity error is detected on the secondary bus. |
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