PI7C7100 datasheet(3/132 Pages) PERICOM

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PI7C7100

3-Port PCI Bridge

ADVANCE INFORMATION

09/18/00

Rev 1.1

Introduction/Product Features ............................................................................................................................... 1

PI7C7100 Block Diagram ...................................................................................................................................... 3

Signal Definitions ................................................................................................................................................... 4

3.1

Signal Types ............................................................................................................................................................ 4

3.2

Signals ...................................................................................................................................................................... 4

3.2.1

Primary Bus Interface Signals .................................................................................................................................. 4

3.2.2

Secondary Bus Interface Signals ............................................................................................................................. 6

3.2.3

Clock Signals ............................................................................................................................................................ 8

3.2.4

Miscellaneous Signals ............................................................................................................................................. 8

3.2.5

JTAG Boundary Scan Signals .................................................................................................................................. 9

3.2.6

Power and Ground .................................................................................................................................................... 9

3.3

PI7C7100 PBGA Pin Listing ..................................................................................................................................... 9

PCI Bus Operation ................................................................................................................................................ 13

4.1

Types of Transactions ........................................................................................................................................... 13

4.2

Single Address Phase ............................................................................................................................................ 14

4.3

Device Select (DEVSEL#) Generation .................................................................................................................... 14

4.4

Data Phase ............................................................................................................................................................. 14

4.5

Write Transactions ................................................................................................................................................ 14

4.5.1

Posted Write Transactions .................................................................................................................................... 14

4.5.2

Memory Write and Invalidate Transactions .......................................................................................................... 15

4.5.3

Delayed Write Transactions .................................................................................................................................. 15

4.5.4

Write Transaction Address Boundaries ................................................................................................................ 16

4.5.5

Buffering Multiple Write Transactions .................................................................................................................. 16

4.5.6

Fast Back-to-Back Write Transactions .................................................................................................................. 16

4.6

Read Transactions ................................................................................................................................................. 17

4.6.1

Prefetchable Read Transactions ............................................................................................................................ 17

4.6.2

Non-prefetchable Read Transactions .................................................................................................................... 17

4.6.3

Read Pre-fetch Address Boundaries ...................................................................................................................... 17

4.6.4

Delayed Read Requests ......................................................................................................................................... 18

4.6.5

Delayed Read Completion with Target .................................................................................................................. 18

4.6.6

Delayed Read Completion on Initiator Bus ........................................................................................................... 18

4.7

Configuration Transactions ................................................................................................................................... 19

4.7.1

Type 0 Access to PI7C7100 ................................................................................................................................... 19

4.7.2

Type 1 to Type 0 Conversion ................................................................................................................................ 20

4.7.3

Type 1 to Type 1 Forwarding ................................................................................................................................ 21

4.7.4

Special Cycles ........................................................................................................................................................ 22

4.8

Transaction Termination ........................................................................................................................................ 22

4.8.1

Master Termination Initiated by PI7C7100 ............................................................................................................ 23

4.8.2

Master Abort Received by PI7C7100 ..................................................................................................................... 23

4.8.3

Target Termination Received by PI7C7100 ............................................................................................................ 24

4.8.3.1

Delayed Write Target Termination Response ....................................................................................................... 24

4.8.3.2 Posted Write Target Termination Response ......................................................................................................... 24

4.8.3.3 Delayed Read Target Termination Response ........................................................................................................ 25

4.8.4

Target Termination Initiated by PI7C7100 ............................................................................................................. 26

4.8.4.1 Target Retry ........................................................................................................................................................... 26

4.8.4.2 Target Disconnect .................................................................................................................................................. 27

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