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XRT73L03IV Datasheet(PDF) 39 Page - Exar Corporation |
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XRT73L03IV Datasheet(HTML) 39 Page - Exar Corporation |
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39 / 62 page ![]() áç áç áç áç 3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT XRT73L03 PRELIMINARY REV. P1.0.13 36 ceive a line signal with an overall cable length of 300 feet or greater. Conversely, turn OFF the Receive Equalizer if the Receive Section of a given channel is going to receive a line signal over a cable length of less than 300 feet. NOTES: 1. If the Receive Equalizer block is turned ON when it is receiving a line signal over short cable length the received line signal may be over-equalized, which could degrade performance by increasing the amount of jitter that exists in the recovered data and clock signals or by creating bit-errors. 2. The Receive Equalizer has been designed to counter the frequency-dependent cable loss that a line signal experiences as it travels from the trans- mitting terminal to the receiving terminal. However, the Receive Equalizer was not designed to counter flat loss where all of the Fourier frequency compo- nents within the line signal are subject to the same amount of attenuation. Flat loss is handled by the AGC block. Disable the Receive Equalizer block by doing either of the following: a. Operating in the Hardware Mode Set the REQEN(n) input pin "Low". b. Operating in the HOST Mode Write a "0" to the REQEN(n) bit-field in Command Register CR2. 3.3 CLOCK RECOVERY PLL The purpose of the Clock Recovery PLL is to track the incoming Dual-Rail data stream and to derive and generate a recovered clock signal. It is important to note that the Clock Recovery PLL re- quires a line rate clock signal at the ExClk input pin. The Clock Recovery PLL operates in one of two modes: • The Training Mode • The Data/Clock Recovery Mode 3.3.1 The Training Mode If a given channel in the XRT73L03 is not receiving a line signal via the RTIP and RRing input pins, or if the frequency difference between the line signal and that applied via the ExClk input pin exceeds 0.5%, the channel operates in the Training Mode. When the channel is operating in the Training Mode, it does the following: a. Declare a Loss of Lock indication by toggling its respective RLOL(n) output pin “High". b. Output a clock signal via the RxClk(n) output pin which is derived from the signal applied to the EXClk(n) input pin. 3.3.2 The Data/Clock Recovery Mode If the frequency difference between the line signal and that applied via the ExClk input pin is less than 0.5%, the channel operates in the Data/Clock Recov- ery mode. In this mode, the Clock Recovery PLL locks onto the line signal via the RTIP and RRing in- put pins. 3.4 THE HDB3/B3ZS DECODER The Remote Transmitting Terminal typically encodes the line signal into some sort of Zero Suppression Line Code (e.g., HDB3 for E3 and B3ZS for DS3 and STS-1). The purpose of this encoding activity was to aid in the Clock Recovery process of this data from the Near-End Receiving Terminal. However, once the data has made it across the E3, DS3 or STS-1 Trans- port Medium and has been recovered by the Clock Recovery PLL, it is now necessary to restore the orig- inal content of the data. Hence, the purpose of the HDB3/B3ZS Decoding block is to restore the data transmitted over the E3, DS3 or STS-1 line to its orig- inal content prior to Zero Suppression Coding. 3.4.1 B3ZS Decoding DS3/STS-1 Applications If the XRT73L03 is configured to operate in the DS3 or STS-1 Modes, then the HDB3/B3ZS Decoding Blocks perform B3ZS Decoding. When the Decoders are operating in this mode, each of the Decoders parses through its respective incoming Dual-Rail data and checks for the occurrence of either a "00V" or a "B0V" pattern. If the B3ZS Decoder detects this par- ticular pattern, it substitutes these bits with a "000" pattern. NOTE: If the B3ZS Decoder detects any bipolar violations that is not in accordance with theB3ZS Line Code format or if the B3ZS Decoder detects a string of 3 or more consecu- tive "0’s" in the incoming line signal, the B3ZS Decoder COMMAND REGISTER CR2_(N) D4 D3 D2 D1 D0 RESERVED ENDECDIS(n) ALOSDIS(n) DLOSDIS(n) REQEN(n) XX X X 0 |
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