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CY2287
7
Switching Waveforms
Notes:
13. Once the PWR_DWN signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest will be held LOW on the next HIGH-to-LOW
transition.
14. Waveforms are not to scale.
15. Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
Duty Cycle Timing
t1A
t1B
All Outputs Rise/Fall Time
OUTPUT
t2
VDD
0V
t3
CLK-CLK Output Skew
t4
CLKA
CLKB
Cycle-Cycle Clock Jitter
CLK
t8A
t8B
PWR_DOWN
CPUCLK
Peripheral
PWR_DWN
VCO
Crystal
Clocks
[13, 14, 15]
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