GD25VE32CSIS datasheet(20/63 Pages) GIGADEVICE

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Uniform Sector

Dual and Quad Serial Flash

GD25VE32C

7.9. Quad Output Fast Read (6BH)

The Quad Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, and each bit is

latched in on the rising edge of SCLK, then the memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1

and IO0. The command sequence is shown in followed Figure10. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable bit

(QE) of Status Register (S9) must be set to enable for the Quad Output Fast Read command.

Figure 10. Quad Output Fast Read Sequence Diagram

7.10.

Dual I/O Fast Read (BBH)

The Dual I/O Fast Read command is similar to the Dual Output Fast Read command but with the capability to input

the 3-byte address (A23-

0) and a “Continuous Read Mode” byte 2-bit per clock by SI and SO, and each bit is latched in on

the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The command

sequence is shown in followed Figure11. The first byte addressed can be at any location. The address is automatically

incremented to the next higher address after each byte of data is shifted out.

Dual I/O Fast Read with

“Continuous Read Mode”

The Dual I/O Fast Read command

can further reduce command overhead through setting the “Continuous Read Mode”

bits (M7-4) after the input 3-byte address (A23-A0).

If the “Continuous Read Mode” bits (M5-4) = (1, 0), then the next Dual

I/O Fast Read command (after CS# is raised and then lowered) does not require the BBH command code. The command

sequence is shown in followed Figure12.

If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command

requires the command code, thus returning

to normal operation. A “Continuous Read Mode” Reset command can be used

to reset (M5-4) before issuing normal command.

Command

6BH

CS#

SCLK

SI(IO0)

SO(IO1)

High-Z

9 10

28 29 30 31

23 22 21

24-bit address

34 35 36 37

38 39

Byte1

42 43 44 45

46 47

Dummy Clocks

WP#(IO2)

High-Z

HOLD#(IO3)

High-Z

CS#

SCLK

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

Byte2 Byte3 Byte4

GD25VE32CSIS Datasheet(PDF) 20 Page - GigaDevice Semiconductor (Beijing) Inc.

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