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CD4017BMS Datasheet(PDF) 7 Page - Renesas Technology Corp |
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CD4017BMS Datasheet(HTML) 7 Page - Renesas Technology Corp |
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7 / 10 page ![]() CD4017BMS, CD4022BMS FN3297 Rev 0.00 Page 7 of 10 August 1998 FIGURE 2. CD4022BMS Timing Diagram FIGURE 3. CD4017BMS FIGURE4. CD4022BMS Logic Diagram (Continued) D C Q1 Q1 R *RESET 15 12 5 4 7 3 1 2 01 2 3 4 11 567 CARRY OUT D C Q2 Q2 R D C Q3 Q3 R D C Q4 Q4 R 14 *CLOCK 13 *CLOCK VDD VSS * All Inputs Protected by CMOS Protection Network 10 INHIBIT CLOCK RESET CLOCK INHIBIT “0” “1” “2” “3” “4” “5” “6” “7” “8” “9” CARRY OUT 00 1 1 22 3 4 5 6 7 8 9 CLOCK RESET CLOCK INHIBIT “0” “1” “2” “3” “4” “5” “6” “7” CARRY OUT 00 0 11 22 33 44 55 66 77 |
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