PIC18F44800TESLASHML datasheet(443/484 Pages) MICROCHIP

443 / 484 page

 2004 Microchip Technology Inc.

Preliminary

DS39637A-page 441

PIC18F2480/2580/4480/4580

FIGURE 27-12:

EXAMPLE SPI™ MASTER MODE TIMING (CKE = 0)

TABLE 27-14: EXAMPLE SPI™ MODE REQUIREMENTS (MASTER MODE, CKE = 0)

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

75, 76

MSb

LSb

bit 6 - - - - - -1

LSb In

bit 6 - - - -1

Note:

Refer to Figure 27-4 for load conditions.

MSb In

Param

No.

Symbol

Characteristic

Min

Max Units

Conditions

TSSL2SCH,

TSSL2SCL

↓ to SCK ↓ or SCK ↑ Input

TCY

—ns

TSCH

SCK Input High Time

(Slave mode)

Continuous

1.25 TCY + 30

—

71A

Single Byte

—

(Note 1)

TSCL

SCK Input Low Time

(Slave mode)

Continuous

1.25 TCY + 30

—

72A

Single Byte

—

(Note 1)

TDIV2SCH,

TDIV2SCL

Setup Time of SDI Data Input to SCK Edge

100

—

73A

TB2B

Last Clock Edge of Byte 1 to the 1st Clock Edge

of Byte 2

1.5 TCY + 40

—

(Note 2)

TSCH2DIL,

TSCL2DIL

Hold Time of SDI Data Input to SCK Edge

100

—

TDOR

SDO Data Output Rise Time

PIC18FXXXX

—

PIC18LFXXXX

—

VDD = 2.0V

TDOF

SDO Data Output Fall Time

—

TSCR

SCK Output Rise Time

(Master mode)

PIC18FXXXX

—

PIC18LFXXXX

—

VDD = 2.0V

TSCF

SCK Output Fall Time (Master mode)

—

TSCH2DOV,

TSCL2DOV

SDO Data Output Valid after

SCK Edge

PIC18FXXXX

—

PIC18LFXXXX

—

100

VDD = 2.0V

Note 1:

Requires the use of Parameter #73A.

Only if Parameter #71A and #72A are used.

PIC18F44800TE/ML Datasheet(PDF) 443 Page - Microchip Technology

PIC18F44800TE/ML Datasheet(HTML) 443 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL