PIC18F44800TESLASHML datasheet(54/484 Pages) MICROCHIP

54 / 484 page

PIC18F2480/2580/4480/4580

DS39637A-page 52

Preliminary

 2004 Microchip Technology Inc.

PIE2

2480 2580 4480 4580

00-0 0000

uu-u uuuu

2480 2580 4480 4580

0--0 000-

u--u uuu-

IPR1

2480 2580 4480 4580

1111 1111

uuuu uuuu

2480 2580 4480 4580

-111 1111

-uuu uuuu

PIR1

2480 2580 4480 4580

0000 0000

uuuu uuuu(1)

2480 2580 4480 4580

-000 0000

-uuu uuuu

PIE1

2480 2580 4480 4580

0000 0000

uuuu uuuu

2480 2580 4480 4580

-000 0000

-uuu uuuu

OSCTUNE

2480 2580 4480 4580

--00 0000

--uu uuuu

TRISE

2480 2580 4480 4580

0000 -111

uuuu -uuu

TRISD

2480 2580 4480 4580

1111 1111

uuuu uuuu

TRISC

2480 2580 4480 4580

1111 1111

uuuu uuuu

TRISB

2480 2580 4480 4580

1111 1111

uuuu uuuu

TRISA(5)

2480 2580 4480 4580

1111 1111(5)

uuuu uuuu(5)

LATE

2480 2580 4480 4580

---- -xxx

---- -uuu

LATD

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

LATC

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

LATB

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

LATA(5)

2480 2580 4480 4580

xxxx xxxx(5)

uuuu uuuu(5)

PORTE

2480 2580 4480 4580

---- x000

---- uuuu

PORTD

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

PORTC

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

PORTB

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

PORTA(5)

2480 2580 4480 4580

xx0x 0000(5)

uu0u 0000(5)

uuuu uuuu(5)

ECANCON

2480 2580 4480 4580

0001 0000

uuuu uuuu

TXERRCNT

2480 2580 4480 4580

0000 0000

uuuu uuuu

RXERRCNT

2480 2580 4480 4580

0000 0000

uuuu uuuu

COMSTAT

2480 2580 4480 4580

0000 0000

uuuu uuuu

CIOCON

2480 2580 4480 4580

--00 ----

--uu ----

BRGCON3

2480 2580 4480 4580

00-- -000

uu-- -uuu

BRGCON2

2480 2580 4480 4580

0000 0000

uuuu uuuu

BRGCON1

2480 2580 4480 4580

0000 0000

uuuu uuuu

TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET

Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1:

One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

See Table 4-3 for Reset value for specific condition.

Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

PIC18F44800TE/ML Datasheet(PDF) 54 Page - Microchip Technology

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