PIC18F44800TESLASHML datasheet(55/484 Pages) MICROCHIP

55 / 484 page

 2004 Microchip Technology Inc.

Preliminary

DS39637A-page 53

PIC18F2480/2580/4480/4580

CANCON

2480 2580 4480 4580

1000 000-

uuuu uuu-

CANSTAT

2480 2580 4480 4580

100- 000-

uuu- uuu-

RXB0D7

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB0D6

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB0D5

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB0D4

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB0D3

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB0D2

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB0D1

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB0D0

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB0DLC

2480 2580 4480 4580

-xxx xxxx

-uuu uuuu

RXB0EIDL

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB0EIDH

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB0SIDL

2480 2580 4480 4580

xxxx x-xx

uuuu u-uu

RXB0SIDH

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB0CON

2480 2580 4480 4580

000- 0000

uuu- uuuu

RXB1D7

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB1D6

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB1D5

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB1D4

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB1D3

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB1D2

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB1D1

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB1D0

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB1DLC

2480 2580 4480 4580

-xxx xxxx

-uuu uuuu

RXB1EIDL

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB1EIDH

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB1SIDL

2480 2580 4480 4580

xxxx x-xx

uuuu u-uu

RXB1SIDH

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

RXB1CON

2480 2580 4480 4580

000- 0000

uuu- uuuu

TXB0D7

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

TXB0D6

2480 2580 4480 4580

xxxx xxxx

uuuu uuuu

TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET

Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1:

One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

See Table 4-3 for Reset value for specific condition.

Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.

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