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PIC18F44800TE/ML Datasheet(PDF) 469 Page - Microchip Technology |
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PIC18F44800TE/ML Datasheet(HTML) 469 Page - Microchip Technology |
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469 / 484 page  2004 Microchip Technology Inc. Preliminary DS39637A-page 467 PIC18F2480/2580/4480/4580 INDEX A A/D ................................................................................... 247 A/D Converter Interrupt, Configuring ....................... 251 Acquisition Requirements ........................................ 252 ADCON0 Register .................................................... 247 ADCON1 Register .................................................... 247 ADCON2 Register .................................................... 247 ADRESH Register ............................................ 247, 250 ADRESL Register .................................................... 247 Analog Port Pins, Configuring .................................. 254 Associated Registers ............................................... 256 Automatic Acquisition Time ...................................... 253 Calculating the Minimum Required Acquisition Time .............................................. 252 Configuring the Module ............................................ 251 Conversion Clock (TAD) ........................................... 253 Conversion Status (GO/DONE Bit) .......................... 250 Conversions ............................................................. 255 Converter Characteristics ........................................ 450 Operation in Power Managed Modes ...................... 254 Special Event Trigger (CCP1) .................................. 256 Special Event Trigger (ECCP) ................................. 174 Use of the CCP1 Trigger .......................................... 256 Absolute Maximum Ratings ............................................. 417 AC (Timing) Characteristics ............................................. 432 Load Conditions for Device Timing Specifications ....................................... 433 Parameter Symbology ............................................. 432 Temperature and Voltage Specifications ................. 433 Timing Conditions .................................................... 433 Access Bank ...................................................................... 70 Mapping with Indexed Literal Offset Mode ................. 94 ACKSTAT ........................................................................ 217 ACKSTAT Status Flag ..................................................... 217 ADCON0 Register ............................................................ 247 GO/DONE Bit ........................................................... 250 ADCON1 Register ............................................................ 247 ADCON2 Register ............................................................ 247 ADDFSR .......................................................................... 404 ADDLW ............................................................................ 367 ADDULNK ........................................................................ 404 ADDWF ............................................................................ 367 ADDWFC ......................................................................... 368 ADRESH Register ............................................................ 247 ADRESL Register .................................................... 247, 250 Analog-to-Digital Converter. See A/D. and BSR ............................................................................. 94 ANDLW ............................................................................ 368 ANDWF ............................................................................ 369 Assembler MPASM Assembler .................................................. 411 Auto-Wake-up on Sync Break Character ......................... 240 B Bank Select Register (BSR) ............................................... 67 Baud Rate Generator ....................................................... 213 Baud Rate Generator (BRG) ............................................ 231 BC .................................................................................... 369 BCF .................................................................................. 370 BF .................................................................................... 217 BF Status Flag ................................................................. 217 Bit Timing Configuration Registers BRGCON1 ............................................................... 338 BRGCON2 ............................................................... 338 BRGCON3 ............................................................... 338 Block Diagrams A/D ........................................................................... 250 Analog Input Model .................................................. 251 Baud Rate Generator .............................................. 213 CAN Buffers and Protocol Engine ........................... 274 Capture Mode Operation ......................................... 166 Comparator I/O Operating Modes ........................... 258 Comparator Output .................................................. 260 Comparator Voltage Reference ............................... 264 Compare Mode Operation ....................................... 167 Device Clock .............................................................. 28 Enhanced PWM ....................................................... 175 EUSART Receive .................................................... 238 EUSART Transmit ................................................... 236 External Power-on Reset Circuit (Slow VDD Power-up) ........................................ 43 Fail-Safe Clock Monitor ........................................... 355 Generic I/O Port ....................................................... 129 High/Low-Voltage Detect with External Input .......... 268 MSSP (I2C Master Mode) ........................................ 211 MSSP (I2C Mode) .................................................... 196 MSSP (SPI Mode) ................................................... 187 On-Chip Reset Circuit ................................................ 41 PIC18F2480/2580 ..................................................... 10 PIC18F4480/4580 ..................................................... 11 PLL (HS Mode) .......................................................... 25 PORTD and PORTE (Parallel Slave Port) ............... 144 PWM Operation (Simplified) .................................... 169 Reads from Flash Program Memory ......................... 99 Single Comparator ................................................... 259 Table Read Operation ............................................... 95 Table Write Operation ............................................... 96 Table Writes to Flash Program Memory .................. 101 Timer0 in 16-Bit Mode ............................................. 148 Timer0 in 8-Bit Mode ............................................... 148 Timer1 ..................................................................... 152 Timer1 (16-Bit Read/Write Mode) ............................ 152 Timer2 ..................................................................... 158 Timer3 ..................................................................... 160 Timer3 (16-Bit Read/Write Mode) ............................ 160 Voltage Reference Output Buffer Example ............. 265 Watchdog Timer ...................................................... 352 Block Diagrams Comparator Analog Input Model ............ 261 BN .................................................................................... 370 BNC ................................................................................. 371 BNN ................................................................................. 371 BNOV .............................................................................. 372 BNZ ................................................................................. 372 BOR. See Brown-out Reset. BOV ................................................................................. 375 BRA ................................................................................. 373 BRG. See Baud Rate Generator. Brown-out Reset (BOR) ..................................................... 44 Disabling in Sleep Mode ............................................ 44 BSF .................................................................................. 373 BTFSC ............................................................................. 374 BTFSS ............................................................................. 374 BTG ................................................................................. 375 BZ .................................................................................... 376 |
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