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PIC18F44800TE/ML Datasheet(PDF) 188 Page - Microchip Technology |
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PIC18F44800TE/ML Datasheet(HTML) 188 Page - Microchip Technology |
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188 / 484 page  PIC18F2480/2580/4480/4580 DS39637A-page 186 Preliminary 2004 Microchip Technology Inc. TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP1 MODULE AND TIMER1 TO TIMER3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49 RCON IPEN SBOREN — RI TO PD POR BOR 50 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 52 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 52 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 52 IPR2 OSCFIP CMIP(3) — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(3) 51 PIR2 OSCFIF CMIF(3) — EEIF BCLIF HLVDIF TMR3IF ECCP1IF(3) 51 PIE2 OSCFIE CMIE(3) — EEIE BCLIE HLVDIE TMR3IE ECCP1IE(3) 52 TRISB PORTB Data Direction Register 52 TRISC PORTC Data Direction Register 52 TRISD(1) PORTD Data Direction Register 52 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 50 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 50 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50 TMR2 Timer2 Module Register 50 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50 PR2 Timer2 Period Register 50 TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register 51 TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register 51 T3CON RD16 T3ECCP1(1) T3CKPS1 T3CKPS0 T3CCP1(1) T3SYNC TMR3CS TMR3ON 51 ECCPR1L(2) Enhanced Capture/Compare/PWM Register 1 (LSB) 51 ECCPR1H(2) Enhanced Capture/Compare/PWM Register 1 (MSB) 51 ECCP1CON(2) EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 51 ECCP1AS(2) ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 51 ECCP1DEL(2) PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 51 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation. Note 1: These bits are available on PIC18F4X80 devices only. 2: These bits or registers are unimplemented in PIC18F2X80 devices; always maintain these bit clear. 3: These bits are available on PIC18F4X80 and reserved on PIC18F2X80 devices. |
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