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Clock

Generation

SYNC

Slicer

SYNC

Separator

5MHz

CLK

Polarity

Detect

SOG

Phase

Select

ADC

DIV

HSYNC

VSYNC

COAST

Activity

Detect

Activity

Detect

DATACLK

SOGOUT

VSOUT

COAST

HSYNC

Activity

Detect

HSOUT

Timing

TVP7000

SLES143 – SEPTEMBER 2005

Figure 5. Sync Processing

The TVP7000 supports RGB/YCbCr 4:4:4 and YCbCr 4:2:2 modes. Output timing is shown in Figure 6. All timing

diagrams are shown for operation with internal PLL clock at phase 0. For a 4:2:2 mode, CbCr data outputs at

BOUT[9:0] pins.

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