STM32L4A6XG datasheet(51/282 Pages) STMICROELECTRONICS

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DS11584 Rev 8

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STM32L4A6xG

Functional overview

3.29.4

Low-power timer (LPTIM1 and LPTIM2)

The devices embed two low-power timers. These timers have an independent clock and are

running in Stop mode if they are clocked by LSE, LSI or an external clock. They are able to

wakeup the system from Stop mode.

LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.

LPTIM2 is active in Stop 0 and Stop 1 mode.

This low-power timer supports the following features:

•

16-bit up counter with 16-bit autoreload register

•

16-bit compare register

•

Configurable output: pulse, PWM

•

Continuous/ one shot mode

•

Selectable software/hardware input trigger

•

Selectable clock source

–

Internal clock sources: LSE, LSI, HSI16 or APB clock

–

External clock source over LPTIM input (working even with no internal clock

source running, used by pulse counter application).

•

Programmable digital glitch filter

•

Encoder mode (LPTIM1 only)

3.29.5

Infrared interface (IRTIM)

The STM32L4A6xG includes one infrared interface (IRTIM). It can be used with an infrared

LED to perform remote control functions. It uses TIM16 and TIM17 output channels to

generate output signal waveforms on IR_OUT pin.

3.29.6

Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 32 kHz internal RC (LSI) and as it operates independently

from the main clock, it can operate in Stop and Standby modes. It can be used either as a

watchdog to reset the device when a problem occurs, or as a free running timer for

application timeout management. It is hardware or software configurable through the option

bytes. The counter can be frozen in debug mode.

3.29.7

System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

the main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

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