Table 2-2. AC Parameters: All I/O Interfaces

Parameter

Symbol

Direction

Min

Typ

Max Unit Conditions

Power-Up

Delay(2)

tPU

To Crypto

Authentication

100

—

—

µs

Minimum time between VCC > VCC min

prior to measurement of tWLO.

Wake Low

Duration

tWLO

To Crypto

Authentication

60

—

—

µs

Wake High Delay

to Data Comm.

tWHI

To Crypto

Authentication

1500

—

—

µs

SDA should be stable high for this entire

duration.

High Side Glitch

Filter at Active

tHIGNOR

E_A

To Crypto

Authentication

45(1)

—

—

ns

Pulses shorter than this in width will be

ignored by the device, regardless of its

state when active.

Low Side Glitch

Filter at Active

tLIGNORE

_A

To Crypto

Authentication

45(1)

—

—

ns

Pulses shorter than this in width will be

ignored by the device, regardless of its

state when active.

Low Side Glitch

Filter at Sleep

tLIGNORE

_S

To Crypto

Authentication

15(1)

—

—

µs

Pulses shorter than this in width will be

ignored by the device when in sleep mode.

Watchdog

Timeout

tWATCHD

OG

To Crypto

Authentication

0.7

1.3

1.7

s

Time from wake until device is forced into

sleep mode if Config.ChipMode.Bit2 is 0.

7.6

13

17

s

Watchdog time : Config.ChipMode.Bit2 is 0.

Note: 

1.

These parameters are guaranteed through characterization, but not tested.

2.

The power-up delay will be significantly longer if Power-On self test is enabled in the configuration

zone.

2.3.1

AC Parameters: Single-Wire Interface

Figure 2-2. AC Timing Diagram: Single-Wire Interface

t

START

t

ZHI

t

ZLO

Logic Ø

t

START

t

BIT

Logic 1

t

START

t

TURNAROUND

t

START

SDA

Table 2-3. AC Parameters: Single-Wire Interface

ATECC608A

Electrical Characteristics

Datasheet Summary

DS40001977A-page 8