Nexperia

74LVC1G97

Low-power configurable multiple function gate

7. Functional description

Table 4. Function table

H = HIGH voltage level; L = LOW voltage level.

Input

Output

C

B

A

Y

L

L

L

L

L

L

H

L

L

H

L

H

L

H

H

H

H

L

L

L

H

L

H

H

H

H

L

L

H

H

H

H

7.1. Logic configurations

Table 5. Function selection table

Logic function

Figure

2-input MUX

see Fig. 6

2-input AND

see Fig. 7

2-input OR with one input inverted

see Fig. 8

2-input NAND with one input inverted

see Fig. 8

2-input AND with one input inverted

see Fig. 9

2-input NOR with one input inverted

see Fig. 9

2-input OR

see Fig. 10

Inverter

see Fig. 11

Buffer

see Fig. 12

001aae002

1

2

3

6

5

4

Y

C

B

A

B

A

C

Y

Fig. 6. 2-input MUX

001aae003

1

2

3

6

5

4

Y

Y

C

A

A

C

Fig. 7. 2-input AND gate

001aae004

1

2

3

6

5

4

Y

Y

C

A

C

A

Y

C

A

Fig. 8. 2-input NAND gate with input A inverted or

2-input OR gate with input C inverted

001aae005

1

2

3

6

5

4

Y

Y

C

B

C

B

Y

C

B

Fig. 9. 2-input NOR gate with input B inverted or

2-input AND gate with input C inverted

74LVC1G97

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 August 2018

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