AX58100LT datasheet(17/71 Pages) ASIX

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AX58100

EtherCAT Slave Controller

3 Chip Configuration and Memory Map Description

Bootstrap Pins for Chip Configuration

The AX58100 supports five multi-function bootstrap pins (pin 19, 20, 58, 40, and 41) for five hardware

configurations, i.e. external I2C EEPROM size, ESC supported port number, RSTO polarity and integrated port 0/1

PHY media mode; and supports other three multi-function bootstrap pins (pin 42, 52, 66) for the configuration of

port 2 MII signals. User needs to utilize an external resistor to pull up / down these bootstrap pins.

Pins

Signal Name

Description

EEP_SIZE

I2C EEPROM Size

0: 1 Kbit to 16Kbit

1: 32Kbit to 4Mbit

3PORT_MODE

ESC port number

0: 2 ports mode

1: 3 ports mode

RSTO_POL

RSTO Reset Output Polarity

0:Active Low

1:Active High

P0_FIBER

Port 0 PHY media mode

0: Copper mode

1: Fiber mode

P1_FIBER

Port 1 PHY Media mode

0: Copper mode

1: Fiber mode

TX_SH[1]

Port 2 MII TXD Align position

2‘b00: Align with MCLK,

2’b01: Delay 1/4 phase with MCLK

2’b10: Delay 1/2 phase with MCLK

2’b11: Delay 3/4 phase with MCLK

TX_SH[0]

LINK_POL

Port 2 MII LINK Polarity

0:Active Low

1:Active High

Table 3-1: Bootstrap Pins Configuration

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