AX58100LT datasheet(24/71 Pages) ASIX

24 / 71 page

AX58100

EtherCAT Slave Controller

IO[21:16] Driving Select:

0: 4mA

1: 8mA

IO[31:22] Driving Select:

0: 4mA

1: 8mA

Note: When MII port 2 enable, the IO[31:16] pins are forced to MII port 2

Checksum (0x0F - 0x0E)

Bit

Description

15: 0

Checksum

Low byte contains remainder of division of EEPROM offset 0x00 to 0x0D as unsigned number

divided by the polynomial X^8+X^2+X+1 (initial value 0xFF)

For debugging purposes, it is possible to disable the checksum validation with a checksum value

of 0x88A4. Note that NEVER use this for production!

Category 1 Type (0x81 - 0x80)

Bit

Description

15:0

Category 1 Type

MUST be 0x0001

Category 1 Data Size (0x83 - 0x82)

Bit

Description

15:0

Category 1 Data Size (words)

MUST be 0x0021

MCTLR Access Control (0x84)

Bit

Description

3:0

Sync. Source Select

0x0: Always triggered

0x1: Start Of Frame (SOF)

0x2: End Of Frame (EOF)

0x3: SYNC0 signal

0x4: LATCH0 signal

0x5: SYNC1 signal

0x6: LATCH1 signal

0x7: After write access

0x8: Trigger when data value changes

0x9: PDI Chip Select Assert

0xA: PDI Chip Select De-assert

0xB: FUNC Chip Select Assert

0xC: FUNC Chip Select De-assert

0xD: Trigger at start of MFC PWM cycle

Others: Always triggered

ESC Access Enable

0: Writeable with Function Host Interface

1: Writeable with ESC

7:5

Reserved

The Bit Definitions of the other parameters from EEPROM offset 0x85 to 0xC4 are the same as the Bit Definitions

of EEPROM offset 0x84.

AX58100LT Datasheet(PDF) 24 Page - ASIX Electronics Corporation

AX58100LT Datasheet(HTML) 24 Page - ASIX Electronics Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

Datasheet Download

Link URL