10

AX6800x

2/4-Port USB KVM Switch SoC

Copyright © 2015 ASIX Electronics Corporation. All rights reserved.

List of Figures

FIGURE 0-1: TARGET APPLICATION DIAGRAM......................................................................................................... 2

FIGURE 0-2: USB KVM........................................................................................................................................... 3

FIGURE 0-3: COMBO KVM ...................................................................................................................................... 3

FIGURE 0-4: AUDIO USB KVM ............................................................................................................................... 4

FIGURE 0-5: KVM WITH STORAGE .......................................................................................................................... 4

FIGURE 0-6: CASCADE USB KVM........................................................................................................................... 5

FIGURE 0-7: USB BRIDGING .................................................................................................................................... 6

FIGURE 1-1: AX6800X BLOCK DIAGRAM .............................................................................................................. 13

FIGURE 1-2: AX68002 PINOUT DIAGRAM ............................................................................................................. 14

FIGURE 1-3: AX68004 PINOUT DIAGRAM ............................................................................................................. 15

FIGURE 3-1: THE PROGRAM MEMORY MAP OF CPU ............................................................................................. 37

FIGURE 3-2: THE INTERNAL MEMORY MAP OF CPU ............................................................................................. 38

FIGURE 4-1: POWER-UP SEQUENCE TIMING DIAGRAM AND TABLE ....................................................................... 44

FIGURE 4-2: POWER-DOWN SEQUENCE TIMING DIAGRAM AND TABLE ................................................................. 45

FIGURE 4-3: TM_CK[2:0] TIMING DIAGRAM AND TABLE ..................................................................................... 46

FIGURE 4-4: TM_GT[2:0] TIMING DIAGRAM AND TABLE ..................................................................................... 46

FIGURE 4-5: TXD1 AND RXD1 TIMING DIAGRAM ................................................................................................ 47

FIGURE 4-6: HIGH SPEED SPI MASTER CONTROLLER TIMING DIAGRAM AND TABLE ........................................... 49

FIGURE 4-7: HIGH SPEED SPI SLAVE CONTROLLER TIMING DIAGRAM AND TABLE .............................................. 50

FIGURE 4-8: PS2 HOST RECEIVING DATA TIMING DIAGRAM AND TABLE ............................................................. 51

FIGURE 4-9: PS2 HOST SENDING DATA TIMING DIAGRAM AND TABLE................................................................. 51

FIGURE 4-10: BUZZER OUTPUT TIMING DIAGRAM AND TABLE ............................................................................. 52