AX68004LF datasheet(20/57 Pages) ASIX

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AX6800x

2/4-Port USB KVM Switch SoC

Table 1-10: Timers Pin Description

Timers Interface

Pin Name

Type

Pin No

Pin Description

100

TM[2:0]_CK I5

46, 16,

TiMer 2, 1, 0 external Clock input

(8).

TM[2:0]_GT I5

43, 18,

TiMer 2, 1, 0 external GaTe control input

(8).

Note 8: To enable these multi-function pins, please set MP1_10/32/54_PSEL = 1 in HWCFG offset 0x001.

Table 1-11: CPU Debugger Pin Description

CPU Debugger Interface

Pin Name

Type

Pin No

Pin Description

100

DB_DI

I5/PU

CPU DeBugger Data Input (9).

DB_CKO

O5/4m

CPU DeBugger Clock Output (9).

DB_DO

O5/4m

CPU DeBugger Data Output (9).

Note 9: To enable these multi-function pins, please set MP2_31_PSEL = 1 in HWCFG offset 0x002.

Table 1-12: High Speed UART 1 Pin Description

High Speed UART 1 Interface

Pin Name

Type

Pin No

Pin Description

100

RXD1

UART 1 serial Receive Data (10).

TXD1

O5/4m

UART 1 serial Transmit Data (10).

CTS1

UART 1 Clear To Send (11).

DSR1

UART 1 Data Set Ready (11).

RI1

UART 1 Ring Indicator (11).

DCD1

UART 1 Data Carrier Detect (11).

RTS1/DE1

O5/4m

UART 1 Request To Send/ Driver output Enable (12) (13).

DTR1/RE1

O5/4m

UART 1 Data Terminal Ready/Receiver output Enable (12) (13).

Note 10: To enable these multi-function pins, please set MP0_10_PSEL = 1 in HWCFG offset 0x001.

Note 11: To enable these multi-function pins, please set MP2_54/76_PSEL = 1 in HWCFG offset 0x002.

Note 12: To enable these multi-function pins, please set MP0_32_PSEL = 1 in HWCFG offset 0x001.

Note 13: To decide use RTS1/DTR1 or DE1/RE1_n please refer high speed UART register description as below

section.

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