VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC8132

2.488Gb/s 1:32 SONET/SDH Demux

G52250-0, Rev 3.1

Page 3

12/7/00

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Low-Speed Data Interface

The 77.76Mb/s parallel data outputs D[31:0] are clocked out of the VSC8132 on the falling clock edge of

the 77.76MHz output clock (DATA78CLK). The data and clock are TTL levels. The MSB (D31) bit is the first

bit into the serial interface.

Parity Selection

The parity output bit (PARITY) is clocked out on the falling edge of the 77.76MHz clock (DATA78CLK).

This bit indicates the parity of the 32 bits of data along with the frame sync bit. The parity of the output is deter-

mined by the parity select input (PARSEL). When the parity select input is LOW, the output parity is odd. When

the parity select is HIGH, the output parity is even. The parity inputs and outputs are TTL levels. See Figure 2

for output timing relationship.

Framing Logic Interface

When a frame detect occurs and the frame detect inhibit input (OOFN) is set LOW, the frame detect output

(SYNC) is set HIGH on the negative edge of the 77.76MHz clock and on the 3rd set of four A2 bytes at the 32-

bit data output. The frame detect mechanism is inhibited when the frame detect inhibit (OOFN) input is set

HIGH. The frame detect output and frame detect inhibit are TTL levels.

NOTE: The 77.76MHz clock misses one clock cycle during a frame detect. This missed cycle occurs one

clock period before the Sync pulse is set HIGH (see Figure 4).

To use as a framer:

Step 1: Set OOFN LOW

Step 2:Wait for Sync pulse

Step 3:When Sync Pulse goes HIGH, set OOFN HIGH

Chip Reset

Chip reset (RESET) will reset the framing logic so that no frame detection barrel shifting is performed.

Therefore, if the frame detect inhibit input is set high, the chip will act as a simple demux after reset. The reset

should be set high for 16 clock cycles of the high speed clock input. The chip reset is a TTL level.

Alarm Logic Interface

The Loss of Clock (CKALARM) and Loss of Data (DTALARM) alarms monitor the activity of the clock

and data. The Alarm Reset (ALMRESET) input controls the alarm activity. Polling of the alarms signals are ini-

tiated by toggling the Alarm Reset input HIGH and then LOW one time. To reset both alarm outputs, the Alarm

Reset should be toggled HIGH to LOW two times. All alarm logic interface signals are TTL levels.

Supplies

The VSC8132 is specified as a HSPECL/TTL device with a single positive 3.3V supply. Normal operation