3

AT97SC3203

5116AS-TPM–7/05

Table 1. Pin Descriptions

Name

TSSOP Pin #

QFN Pin #

Type

Description

LAD[3:0]

17, 20, 23,

26

30, 27, 24,

21

Input or

Output

LPC Multiplexed Command, Address, Data: Internal pull-ups are

provided.

LFRAME#

22

26

Input

LPC frame: Indicates the start of an LPC cycle, or an abort.

LPCPD#

28

32

Input

Power Down: Indicates that the TPM should prepare for power to

be shut off on the LPC interface. If this pin is unused, it should be

tied to the 3V power supply pin through a resistor.

CLKRUN#

15

19

Input or

Output

PCI Clock Run: Active low output enabling the system LPC clock. If

this pin is unused, it should be tied to ground.

LCLK

21

25

Input

33MHz PCI clock provides timing for all transactions on the PCI

bus.

LRESET#

16

20

Input

PCI signal to reset all devices that reside on the PCI bus.

SERIRQ

27

31

Input or

Output

Serialized Interrupt Request Signal. If the SERIRQ function is

enabled, this pin should be connected to the CPU SERIRQ input,

and the line pulled to the 3V power supply pin through a resistor. If

this pin is unused, it should be tied to the 3V power supply pin

through a resistor.

SB3V

5

3

Input

Standby 3.3V Supply. If no separate standby power supply is

connected to this pin, the pin should be tied directly to the 3V

power supply pin.

3V

10, 19, 24

8, 23, 28

Input

Primary 3.3V DC power supply input rail supplied by the

motherboard. May be referred to as Vcc.

GND

4, 11, 18, 25

2, 9, 22, 29

Input

System ground.

NC

1

39

Output

No connect. This pin may be floated. If the XOR chain I/O test

mode is used, the pin should be tied to ground directly or through a

resistor. Reserved for the SMBus Data I/O function.

NC

2

40

Output

No connect. This pin may be floated. If the XOR chain I/O test

mode is used, the pin should be tied to ground directly or through a

resistor. Reserved for the SMBus Clock Input function.

VNC

3

1

Output

Vendor No Connect, as designated in the PC Client TIS

specification. This pin may be floated. If the XOR chain I/O test

mode is used, the pin should be tied to ground directly or through a

resistor.

GPIO6

6

4

Input or

Output

General Purpose Input/Output. Internal Pull-up Resistor. This pin is

mapped to NV Index TPM_NV_INDEX_GPIO_00 and serves as

the GPIO-Express-00. Default TPM configuration: GPIO Input.

GPIO6 also serves as the XOR chain Output during I/O test mode.

NC

75Input

No Connect. This input pin has an internal pull-down resistor and

may be floated. If the XOR chain I/O test mode is used, the pin

should be tied to the 3V power supply directly or through a resistor.

TestI

8

6

Output

TPM manufacturing test input disabled. This pin may be floated. If

the XOR chain I/O test mode is used, the pin should be tied directly

to ground.

TestBI/BADD

9

7

Input

TestBI and BADD functions disabled. This pin should be tied

directly to ground.