5

AT97SC3203

5116AS-TPM–7/05

Notes:

1. These parameters guaranteed by design.

2. All parameters measured with respect to signal crossing Vtest = 0.4 * VCC unless otherwise noted.

3. The minimum parameter must never be violated under any circumstances unless Lreset# is asserted. If proper CLKRUN#

signaling is observed, the maximum specification can be violated.

Notes:

1. Current as of publication date. Contact Atmel marketing for status update.

2. Also RoHS

Table 3. AC Parameters

Cl = 10pf.; VCC = 3.0 to 3.7V; Temperature = 0 to 70-C

Symbol

Parameter

Min

Nom

Max

Units

Notes

TVAL

CLK to Signal Valid Delay – LAD0-3

2

5

11

nS

Measured at Vtrise = 0.285 * VCC and Vtfal

= 0.615 * VCC. Measured from clk at Vtest =

0.4* VCC; Load = 200.

TON

Float to Active Delay

2

4

nS

TOFF

Active to Float Delay

28

nS

TSU

Input Setup Time to CLK

7

2

nS

TH

Input Hold Time from CLK

0

–500

nS

TRST

Reset Active Time After Power Stable

1

mS

Note 1

TRST-

CLK

Reset Active After CLK Stable

100

mS

Note 1

TRST-

OFF

Reset Active to Output Float Delay

40

nS

Note 1

TCLKIN

CLK Period

29.5

30

31

nS

Note 3

TCLKL

O

CLK Low Duration

13.4

18

nS

Note 2, Note 3

TCLKHI

CLK High Duration

13.4

18

nS

Note 2, Note 3

Table 4. Ordering Information

Package

Operation Range

AT97SC3203-01AC

28A3 (TSSOP)

Commercial (0

° to 70° C)

AT97SC3203-X1AC

28A3 (TSSOP)

Commercial (0

° to 70° C)

AT97SC3203-01MC

40ML1 (QFN)

Commercial (0

° to 70° C)

AT97SC3203-X1MC

40ML1 (QFN)

Commercial (0

° to 70° C)