PCM4108CPAPT datasheet(16/39 Pages) TI

16 / 39 page

PCM4108

SBAS354 − JUNE 2005

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ground. A 0.01

µF bypass capacitor should be placed

between the corresponding high and low reference pins.

An X7R ceramic chip capacitor is recommended for this

purpose. In some cases, a larger capacitor may need to be

placed in parallel with the 0.01

µF capacitor, with the value

of the larger capacitor being dependent upon the

low-frequency power-supply noise present in the system.

Typical values may range from 1

µF to 10µF. Low ESR

tantalum or multilayer ceramic chip capacitors are

recommended. Figure 3 illustrates the recommended

connections for the reference pins.

(1) Capacitor(s) required for each of the four reference pairs.

REF+

(1)

COM1

0.01

µF

0.1

µF

0.1

µF

0.1

µFto 10µF

COM2

REF−

(1)

Figure 3. Recommended Connections for Voltage

Reference and Common-Mode Output Pins

In addition to the reference pins, there are two

common-mode voltage output pins, VCOM1 (pin 64) and

VCOM2 (pin 49). These pins are nominally set to a value

equal to VCC/2 by internal voltage dividers. The VCOM1 pin

is common to both Channels 1, 2, 5, and 6, while the

VCOM2 pin is common to Channels 3, 4, 7, and 8. A 0.1µF

X7R ceramic chip capacitor should be connected between

the common-mode output pin and analog ground. The

common-mode outputs are used primarily to bias external

output circuitry.

SAMPLING MODES

The PCM4108 can operate in one of three sampling

modes: Single Rate, Dual Rate, or Quad Rate. Sampling

modes are selected by using the FS[1:0] bits in Control

and FS1 (pin 37) inputs in Standalone mode.

The Single Rate mode allows sampling frequencies up to

and including 54kHz. The D/A converter performs 128x

oversampling of the input data in Single Rate mode.

The Dual Rate mode allows sampling frequencies greater

than 54kHz, up to and including 108kHz. The D/A

converter performs 64x oversampling of the input data in

Dual Rate mode.

The Quad Rate mode allows sampling frequencies greater

than 108kHz, up to and including 216kHz. The D/A

converter performs 32x oversampling of the input data in

Quad Rate mode.

Refer

Table 1

for

examples

system

clock

requirements for common sampling frequencies.

SYSTEM CLOCK REQUIREMENTS

The PCM4108 requires a system clock, applied at the

SCKI input (pin 19). The system clock operates at an

integer multiple of the input sampling frequency, or fS. The

multiples supported include 128fS, 192fS, 256fS, 384fS,

512fS, or 768fS. The system clock frequency is dependent

upon the sampling mode. Table 1 shows the required

system clock frequencies for common audio sampling

frequencies. Figure 4 shows the system clock timing

requirements.

Although the architecture of the PCM4108 is tolerant to

phase jitter on the system clock, it is recommended that

the user provide a low jitter clock (100ps or less) for optimal

performance.

Table 1. Sampling Modes and System Clock Frequencies for Common Audio Sampling Rates

SAMPLING FREQUENCY, fS

SYSTEM CLOCK FREQUENCY (MHz)

SAMPLING MODE

SAMPLING FREQUENCY, fS

(kHz)

128fS

192fS

256fS

384fS

512fS

768fS

Single Rate

n/a

8.192

12.288

16.384

24.576

Single Rate

44.1

n/a

11.2896

16.9344

22.5792

33.8688

Single Rate

n/a

12.288

18.432

24.576

36.864

Dual Rate

88.2

n/a

22.5792

33.8688

n/a

Dual Rate

n/a

24.576

36.864

n/a

Quad Rate

176.4

22.5792

33.8688

n/a

Quad Rate

192

24.576

36.864

n/a

PCM4108CPAPT Datasheet(PDF) 16 Page - Texas Instruments

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