PCM4108

SBAS354 − JUNE 2005

www.ti.com

22

SUBA

DGND

V

DD

PCM4108

(a) TDM Formats, Single or Dual Rate Sampling Modes.

SUBB

Ch. 1−8

LRCK

BCK

DATA0

DATA2

DSP

Decoder,

or Logic

SCKI

Clock

SUBA

DGND

PCM4108

(b) TDM Formats, Quad Rate Sampling Mode.

SUBB

Ch. 1−4

Ch. 5−8

LRCK

BCK

DATA0

DATA2

DSP

Decoder,

or Logic

SCKI

Clock

Figure 12. TDM Connection

LRCK

Normal, Zero BCK Delay

LRCK

Normal, One BCK Delay

LRCK

Inverted, Zero BCK Delay

LRCK

Inverted, One BCK Delay

Audio Data applied

to both DATA0 and DATA2

Slot 1

Slot 2

Slot 3

Slot 4

Slot 5

Slot 6

Slot 7

Slot 8

Ch.1

Ch.2

Ch.3

Ch.4

Ch.5

Ch.6

Ch.7

Ch. 8

Sub−Frame 0

(SUBA = 0)

Sub−Frame 1

(SUBB = 1)

One Frame

BCK = 192f

In the case of BCK = 192f

In the case of BCK = 256f

The audio data is left justified in the time slot, with the least significant 8 bits of each time slot being don’tcare bits.

Audio data is always presented in two’s complement, MSB−first format.

TDM Data Formats

− Single and Dual Rate Sampling Modes

Figure 13. TDM Data Formats: Single and Dual Rate Sampling Modes