PCM4108CPAPT datasheet(20/39 Pages) TI

20 / 39 page

PCM4108

SBAS354 − JUNE 2005

www.ti.com

AUDIO SERIAL PORT

The audio serial port provides a common interface to

digital signal processors, digital interface receivers (AES3,

S/PDIF), and other digital audio devices. The port

operates as a slave to the processor, receiver, or other

clock generation circuitry. Figure 9 illustrates a typical

audio serial port connection to a processor or receiver. The

audio serial port is comprised of six signal pins: BCK (pin

20), LRCK (pin 21), DATA0 (pin 22), DATA1 (pin 23),

DATA2 (pin 24), and DATA3 (pin 25).

LRCK

BCK

DATA0

DATA1

DATA2

DATA3

FSX

CLKX

DX0

DX1

DX2

DX3

System Clock

PCM4108

DSP

SCKI

Figure 9. Audio Serial Port Connections for Left-

Justified, Right-Justified, and I2S Formats

The LRCK pin functions as either the left/right word clock

or the frame synchronization clock, depending upon the

data format selected. The LRCK frequency is equal to the

input sampling frequency (44.1kHz, 48kHz, 96kHz, etc.).

The BCK pin functions as the serial data clock input. This

input is referred to as the bit clock. The bit clock runs at an

integer multiple of the input sampling frequency. Typical

multiples include 32, 48, 64, 96, 128, 192, and 256,

depending upon the data format, word length, and system

clock frequency selected.

The DATA0, DATA1, DATA2, and DATA3 pins are the

audio data inputs. When using Left-Justified, Right-

Justified, or I2S data formats, the DATA0 pin carries the

audio data for channels 1 and 2, the DATA1 pin carries the

audio data for channels 3 and 4. The DATA2 pin carries

audio data for channels 5 and 6, and the DATA3 pin carries

audio data for channels 7 and 8.

When using TDM data formats, the data input pins are

re-defined. When using Single or Dual Rate sampling

modes, DATA0 and DATA2 are connected together. All

eight channels are carried on a single data connection,

with the SUBA (pin 17) and SUBB (pin 18) inputs

determining the subframe utilized to source the data for

channel Bank A (channels 1−4), or channel Bank B

(channels 5−8). Refer to Figure 13 for frame details. When

using TDM formats with Quad Rate sampling, both SUBA

and SUBB are forced low. DATA0 serves as the data input

for channels 1−4, while DATA2 serves as the input for

channels 5−8. Refer to Figure 14 for frame details.

The audio serial port data formats are shown in Figure 10,

Figure 13, and Figure 14. Data formats are selected by

using the FMT[2:0] bits in Control Register 7 in Software

mode, or by using the FMT0 (pin 33), FMT1 (pin 34), and

FMT2 (pin 35) inputs in Standalone mode. In Software

mode, the user may also select the phase (normal or

inverted) for the LRCK input, as well as the data sampling

edge for the BCK input (either rising or falling edge). The

reset default conditions for the Software mode are normal

phase for LRCK and rising edge data sampling for BCK.

The PCM audio data must be binary two’s complement,

MSB first for all data formats.

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