LPC55S2X datasheet(56/126 Pages) NXP

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LPC55S2x/LPC552x

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Product data sheet

Rev. 1.8 — 4 March 2020

56 of 126

NXP Semiconductors

LPC55S2x/LPC552x

32-bit ARM Cortex-M33 microcontroller

and/or receivers can operate in either master or slave mode, depending on whether the

chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and

can be controlled by more than one bus master connected to it.

Features

• Support standard, Fast-mode, and Fast-mode Plus (specific I2C pins) with data rates

of up to 1 Mbit/s.

• Support high-speed slave mode with data rates of up to 3.4 Mbit/s (specific I2C pins).

• Independent Master, Slave, and Monitor functions.

• Supports both Multi-master and Multi-master with Slave functions.

• Multiple I2C slave addresses supported in hardware.

• One slave address can be selectively qualified with a bit mask or an address range in

order to respond to multiple I2C-bus addresses.

• 10-bit addressing supported with software assist.

• Supports SMBus.

• Separate DMA requests for master, slave, and monitor functions.

• No chip clocks are required in order to receive and compare an address as a slave, so

this event can wake-up the device from deep-sleep mode.

• Automatic modes optionally allow less software overhead for some use cases.

7.23.3.4 USART

Features

• Maximum bit rates of 6.25 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous

mode for USART functions.

• 7, 8, or 9 data bits and 1 or 2 stop bits.

• Synchronous mode with master or slave operation. Includes data phase selection and

continuous clock option.

• Multiprocessor/multidrop (9-bit) mode with software address compare.

• RS-485 transceiver output enable.

• Autobaud mode for automatic baud rate detection

• Parity generation and checking: odd, even, or none.

• Software selectable oversampling from 5 to 16 clocks in asynchronous mode.

• One transmit and one receive data buffer.

• RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

• Received data and status can optionally be read from a single register

• Break generation and detection.

• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

• Built-in Baud Rate Generator with auto-baud function.

• A fractional rate divider is shared among all USARTs.

LPC55S2X Datasheet(PDF) 56 Page - NXP Semiconductors

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