UPD360 datasheet(202/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 202

 2016-2017 Microchip Technology Inc.

15.0

WATCHDOG TIMER (WDT)

15.1

General Description

The function of the Watchdog Timer (WDT) is to provide a mechanism to detect if the device has failed.

When enabled, the Watchdog Timer circuit will generate a WDT initiated system reset if the user program fails to reload

the WDT within a specified length of time known as the WDT Interval.

The Watchdog timer operates off of the 20 KHz Keep Alive Oscillator or 48 MHz Relaxation Oscillator depending on the

resolution selected by WDT_UNITS bit in Watchdog Control Register (WDT_CTL).

A watchdog timer initiated system reset is indicated by assertion of WDT_INT bit in the Interrupt Enable Register

(INT_EN). In order to clear the WDT_INT bit, the WDT_STS bit in Watchdog Control Register (WDT_CTL) must be

cleared.

15.2

WDT Operation

15.2.1

WDT ACTIVATION MECHANISM

The WDT is activated by the following sequence of operations during normal operation:

Clear the WDT_EN bit of Watchdog Control Register (WDT_CTL).

Load the Watchdog Load Register (WDT_LOAD) with the count value.

Set the WDT_EN bit of Watchdog Control Register (WDT_CTL).

The WDT Activation Mechanism starts the WDT decrementing counter.

15.2.2

WDT DEACTIVATION MECHANISM

The WDT is deactivated by clearing the WDT_EN bit in the Watchdog Control Register (WDT_CTL). The WDT Reload

Mechanism places the WDT in a low power state in which clocks are gated and the counter stops decrementing.

15.2.3

WDT RELOAD MECHANISM

If the WDT is not reloaded within periods that are shorter than the programmed watchdog interval, the WDT will under-

flow, a WDT reset will be generated, and the WDT_STS bit will be set in the Watchdog Control Register (WDT_CTL).

It is the responsibility of software to continually execute sections of code which reload the watchdog timer (WDT), caus-

ing the counter to be reloaded via the WDT Activation Mechanism or writing to the Watchdog Kick Register (WDT_-

KICK).

15.2.4

WDT INTERVAL

The WDT Interval is the time it takes for the WDT to decrements from the Watchdog Load Register (WDT_LOAD) value

to 0h.

15.3

I2C/SPI Writes

When a watchdog interrupt is pending all write operations are blocked until the WDT_STS bit in the Watchdog Control

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