UPD360 datasheet(204/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 204

 2016-2017 Microchip Technology Inc.

15.4.2

WATCHDOG KICK REGISTER (WDT_KICK)

15.4.3

WATCHDOG COUNT REGISTER (WDT_COUNT)

WDT_COUNT[7:0] = 0x4h

WDT_COUNT[15:8] = 0x5h

WDT_COUNT[23:16] = 0x6h

WDT_COUNT[31:24] = 0x7h

Address:

3002h

Size:

8 bits

Bits

Description

Type

Default

7:1

RESERVED

KICK

Writes of any value to this register shall cause the watchdog timer to be imme-

diately reloaded with the value defined in Watchdog Load Register (WDT_-

LOAD) and start decrementing when the WDT_EN bit in the Watchdog

Control Register (WDT_CTL) is set to 1b. Writes to this register when

WDT_EN is 0b have no affect.

Note:

Reads of this register always return 0h.

Note:

Due to clock domain synchronization, several clock cycles may

elapse before this takes affect and the counter reloads.

R/W

Address:

3004h

Size:

32 bits

Bits

Description

Type

Default

31:0

WDT_COUNT

This read only register provides a snapshot of the current state of the timer.

The lower byte shall always be read first. Reading of the lower order byte

results in a snapshot of the counter taken. This ensures that when the upper

bytes are read the state of the counter is remains in sync.

FFFF_FFFFh

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