UPD360 datasheet(144/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 144

 2016-2017 Microchip Technology Inc.

11.4.2.4

RX Minimum Bit-Rate Bit Period Count Register (RX_BIT_PER_CNT_MIN_BR)

The value of this register, together with value of the RX Maximum Bit-Rate Bit Period Count Register

(RX_BIT_PER_CNT_MAX_BR), is used to determine valid bit-time (also referenced as bit-period) of the RX signal.

RX_BIT_PER_CNT_MIN_BR > valid bit time > RX_BIT_PER_CNT_MAX_BR.

11.4.2.5

RX Status Register (RX_STAT)

Address:

1A43h

Size:

8 bits

Bits

Description

Type

Default

7:0

RX_BIT_PER_CNT_MIN_BR

Bit period count at minimum bit-rate.

= (((clock_freq_KHz / min_bit_rate_Kbps) * (100 + tolerance) / 100) - 1)

WARNING: If macros are defined in C code, then math must be arranged so

that integer overflow does not occur.

R/W

00h

Address:

1A44h

Size:

8 bits

Bits

Description

Type

Default

7:2

RESERVED

RX_IN_PROCESS

Receiver is active.

Hardware is receiving a packet, i.e., line is busy and transmitter is not active.

LINE_STATE

0: Line is idle

1: Line is busy (BMC line idle timer indicating line is busy)

If this bit is “1”, a receive might be in progress and software should wait for the

message reception to complete. If it is “0”, software may set the GO bit.

Hardware will take further action until the very last possible moment to avoid

bus contention. Bus contention is still possible and not 100% avoidable.

In cases where hardware takes preventative measures to avoid bus conten-

tion, the TX packet will be aborted. Software will be informed of this via an

interrupt and setting of the TX_ABORTED bit in the TX Interrupt Status Regis-

ter (TX_IRQ_STAT).

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