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RM48L540DPGET Datasheet(PDF) 88 Page - Texas Instruments

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Part # RM48L540DPGET
Description  RM48Lx40 16- and 32-Bit RISC Flash Microcontroller
PDF  174 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

RM48L540DPGET Datasheet(HTML) 88 Page - Texas Instruments

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EMIF_nCS[3:2]
25
Asserted
2
2
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
EMIF_nWE
EMIF_WAIT
SETUP
Extended Due to EMIF_WAIT
28
Deasserted
STROBE
STROBE HOLD
RM48L940, RM48L740, RM48L540
SPNS175C – APRIL 2012 – REVISED JUNE 2015
www.ti.com
Figure 6-16. EMIFnWAIT Write Timing Requirements
Table 6-27. EMIF Asynchronous Memory Timing Requirements
NO.
MIN
NOM
MAX
UNIT
READS AND WRITES
E
EMIF clock period
10
ns
Pulse duration, EMIFnWAIT
2
tw(EM_WAIT)
2E
ns
assertion and deassertion
READS
tsu(EMDV-EMOEH)
Setup time, EMIFDATA[15:0]
12
30
ns
valid before EMIFnOE high
th(EMOEH-EMDIV)
Hold time, EMIFDATA[15:0] valid
13
0.5
ns
after EMIFnOE high
Setup Time, EMIFnWAIT
14
tsu(EMOEL-EMWAIT)
asserted before end of Strobe
4E+30
ns
Phase(1)
WRITES
Setup Time, EMIFnWAIT
28
tsu(EMWEL-EMWAIT)
asserted before end of Strobe
4E+30
ns
Phase(1)
(1)
Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended
wait states. Figure 6-14 and Figure 6-16 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
88
System Information and Electrical Specifications
Copyright © 2012–2015, Texas Instruments Incorporated
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