PIC16F913 datasheet(16/272 Pages) MICROCHIP

16 / 272 page

PIC16F917/916/914/913

DS41250E-page 14

Preliminary

2.2

Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers (GPRs)

and the Special Function Registers (SFRs). Bits RP0

and RP1 are bank select bits.

= 00:

→ Bank 0

= 01:

→ Bank 1

= 10:

→ Bank 2

= 11:

→ Bank 3

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function

Registers

are

the

General

Purpose

Registers,

implemented as static RAM. All implemented banks

contain Special Function Registers. Some frequently

used Special Function Registers from one bank are

mirrored in another bank for code reduction and

quicker access.

2.2.1

GENERAL PURPOSE REGISTER

FILE

The register file is organized as 256 x 8 in the

PIC16F913/914 and 352 x 8 in the PIC16F916/917.

Each register is accessed either directly or indirectly

through the File Select Register (FSR) (see Section 2.5

“Indirect Addressing, INDF and FSR Registers”).

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Tables 2-1,

2-2, 2-3 and 2-4). These registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

associated with the “core” are described in this section.

Those related to the operation of the peripheral

features are described in the section of that peripheral

feature.

RP0

RP1

(STATUS<6:5>)

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