PIC16F916ESLASHP301 datasheet(31/272 Pages) MICROCHIP

31 / 272 page

Preliminary

DS41250E-page 29

PIC16F917/916/914/913

2.3

PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low

byte comes from the PCL register, which is a readable

and writable register. The high byte (PC<12:8>) is not

directly

readable

writable

and

comes

from

PCLATH. On any Reset, the PC is cleared. Figure 2-5

shows the two situations for the loading of the PC. The

upper example in Figure 2-5 shows how the PC is

loaded on a write to PCL (PCLATH<4:0>

→ PCH).

The lower example in Figure 2-5 shows how the PC is

loaded

during

CALL

GOTO

instruction

(PCLATH<4:3>

→ PCH).

FIGURE 2-5:

LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). When perform-

ing a table read using a computed GOTO method, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block). Refer to the

Application Note AN556, “Implementing a Table Read”

(DS00556).

2.3.2

STACK

The

PIC16F917/916/914/913

family

has

8-level x 13-bit wide hardware stack (see Figures 2-1

and 2-2). The stack space is not part of either program

or data space and the Stack Pointer is not readable or

writable. The PC is PUSHed onto the stack when a

CALL

instruction is executed or an interrupt causes a

branch. The stack is POPed in the event of a RETURN,

RETLW

or a RETFIE instruction execution. PCLATH is

not affected by a PUSH or POP operation.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

PUSH overwrites the value that was stored from the

first PUSH. The tenth PUSH overwrites the second

PUSH (and so on).

2.4

Program Memory Paging

All PIC16F917/916/914/913 devices are capable of

addressing a continuous 8K word block of program

memory. The CALL and GOTO instructions provide only

11 bits of address to allow branching within any 2K pro-

gram memory page. When doing a CALL or GOTO

instruction, the upper 2 bits of the address are provided

by PCLATH<4:3>. When doing a CALL or GOTO instruc-

tion, the user must ensure that the page select bits are

programmed so that the desired program memory

page is addressed. If a return from a CALL instruction

(or interrupt) is executed, the entire 13-bit PC is POPed

off

the

stack.

Therefore,

manipulation

the

PCLATH<4:3> bits is not required for the RETURN

instructions (which POPs the address from the stack).

Example 2-1 shows the calling of a subroutine in

page 1 of the program memory. This example assumes

that PCLATH is saved and restored by the Interrupt

Service Routine (if interrupts are used).

EXAMPLE 2-1:

CALL OF A SUBROUTINE

IN PAGE 1 FROM PAGE 0

PCLATH<4:0>

PCLATH

Instruction with

ALU Result

GOTO

, CALL

OPCODE<10:0>

11 10

PCLATH<4:3>

PCH

PCL

PCLATH

PCH

PCL

PCL as

Destination

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL,

RETURN

RETLW

and RETFIE instruc-

tions or the vectoring to an interrupt

address.

Note:

The contents of the PCLATH register are

unchanged after a RETURN or RETFIE

instruction is executed. The user must

rewrite the contents of the PCLATH regis-

ter for any subsequent subroutine calls or

GOTO

instructions.

ORG 0x500

BCF PCLATH,4

BSF PCLATH,3

;Select page 1

;(800h-FFFh)

CALL SUB1_P1

;Call subroutine in

;page 1 (800h-FFFh)

ORG 0x900

;page 1 (800h-FFFh)

SUB1_P1

;called subroutine

;page 1 (800h-FFFh)

RETURN

;return to

;Call subroutine

;in page 0

;(000h-7FFh)

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