AS9C25512M2018L datasheet(19/30 Pages) ALSC

Part #	AS9C25512M2018L

Description	2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface

PDF	30 Pages

Scroll/Zoom	100%

Manufacturer	ALSC [Alliance Semiconductor Corporation]

Direct Link	https://www.alliancememory.com

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19 / 30 page

AS9C25512M2018L

AS9C25256M2018L

9/24/04, v.1.2

Alliance Semiconductor

P. 19 of 30

Collision timing waveform[2]

Notes:

1. Parameters tCYC,tCH and tCL are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics).

2. Chip Selected (CE0 = L and CE1 =H). True for both ports.

3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle.

4. “Am” refers to matched address. “Aa” and “Ab” refer to any other valid address.

5. During address collision the data validity is guaranteed only if tCCO is greater than the minimum specified (Refer AC timing characteristics).

CLKA

ADDRESSA[3]

R/WA

COLA

CLKB

ADDRESSB[3]

R/WB

COLB

tCH[1]

tCYC[1]

tCL[1]

tWS

tAS

tAH

tCH[1]

tCL[1]

tCYC[1]

tAS

tAH

tWS

tWH

tCCO

tSCOL tRCOL

tSCOL

tRCOL

tWH

Don’t care

[5]

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AS9C25512M2018L Datasheet(PDF) 19 Page - Alliance Semiconductor Corporation

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