AS9C25512M2018L datasheet(8/30 Pages) ALSC

8 / 30 page

AS9C25512M2018L

AS9C25256M2018L

9/24/04, v.1.2

Alliance Semiconductor

P. 8 of 30

Byte control truth table[1,2,3,4,5]

Notes:

1. L = low, H = high

2. CE0 = L, CE1 = H (Chip in Select mode)

3. R/W = H for a Read operation, R/W = L for a Write operation

4. Byte 1 - DQ[17:9], Byte 0 - DQ[8:0]

5. More than one byte enable may be simultaneously asserted

Read/write control truth table[1,4]

Notes:

1. L = low, H = high, X = don't care

2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H)

3. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DQn refers to the corresponding Byte

4. Snooze de-asserted (ZZ=L)

5. True in flow-through mode. For Pipeline mode there will be a 1 cycle latency [refer timing diagrams]

6. For a write command issued before the completion of a read command, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time.

7. All DQs are tristated on power-up

8. OE should be asserted (OE = L) (Refer Read timing waveform)

9. In pipeline mode the DQs are HighZ-ed in the same cycle if R/W=L

Counter control truth table[1,2,5,6]

Notes:

1. L = low, H = high, X = don't care

2. Cycle can be Read, Write or Deselect (Controlled by appropriate setting of R/W, CE0, CE1 and BEn)

3. ADS, INC, RPT are independent of all other memory controls including R/W, CE0,CE1 and BEn (i.e Counter works independent of R/W, CE0,CE1 and BEn)

4. The 'Mirror register' used for the Repeat operation is loaded with External address during every valid ADS access. “Am” refers to the mirror register content.

5. Clock to the counter is disabled during Snooze mode (True for both ports).

6. The counter and the mirror registers are not initialized on Power-up (refer Counter description).

BE1

BE0

CLK

Mode

L to H

All Bytes Deselected - NOP

L to H

Read or Write Byte 0

L to H

Read or Write Byte 1

CE[2]

R/W

BEn[3]

CLK

Operation

DQn[0:8][3,7]

L to H

Chip Deselect

Hi-Z[5,9]

L to H

Byte Deselect

Hi-Z[5,9]

L to H

Byte Write

Din[6]

L to H

Byte Read

Qout[5,8]

CLK

ADS[3]

INC[3]

RPT[3]

External

Address

Accessed

Mirror

Content[4]

Address

Accessed

Operation

L to H

Load[4]

L to H

An + 1

Increment

L to H

Hold

L to H

Repeat

AS9C25512M2018L Datasheet(PDF) 8 Page - Alliance Semiconductor Corporation

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