PFS172 datasheet(86/92 Pages) PADAUK

86 / 92 page

PFS172

8bit MTP MCU with 8-bit ADC

Page 86 of 92

PDK-DS-PFS172-EN_V000-May 8, 2020

8. Code Options

Option

Selection

Description

Security

Enable

MTP content is protected and program cannot be read back

Disable

MTP content is not protected so program can be read back

LVR

4.0V

Select LVR = 4.0V

3.5V

Select LVR = 3.5V

3.0V

Select LVR = 3.0V

2.7V

Select LVR = 2.7V

2.5V

Select LVR = 2.5V

2.2V

Select LVR = 2.2V

2.0V

Select LVR = 2.0V

1.8V

Select LVR = 1.8V

Boot-up_Time

Slow

Please refer to tWUP and tSBP in Section 4.1

Fast

Please refer to tWUP and tSBP in Section 4.1

Interrupt Src0

PA.0

INTEN/ INTRQ.Bit0 is from PA.0

PB.5

INTEN/ INTRQ.Bit0 is from PB.5

Interrupt Src1

PB.0

INTEN/ INTRQ.Bit1 is from PB.0

PA.4

INTEN/ INTRQ.Bit1 is from PA.4

PB4_PB7_Drive

Normal

PB4 & PB7 Drive / Sink Current is Normal

Strong

PB4 & PB7 Drive / Sink Current is Strong (ICE does NOT support.)

Comparator

Edge

All_Edge

The comparator will trigger an interrupt on both the rising edge or falling edge

Rising_Edge

The comparator will trigger an interrupt on the rising edge

Falling_Edge

The comparator will trigger an interrupt on the falling edge

GPC_PWM

Disable

Comparator does not control all PWM outputs

Enable

Comparator controls all PWM outputs (ICE does NOT support.)

TMx_Source

16MHZ

When tm2c[7:4]= 0010, TM2 clock source = IHRC = 16MHZ

When tm3c[7:4]= 0010, TM3 clock source = IHRC = 16MHZ

32MHZ

When tm2c[7:4]= 0010, TM2 clock source = IHRC*2 = 32MHZ

When tm3c[7:4]= 0010, TM3 clock source = IHRC*2 = 32MHZ

(ICE does NOT support.)

TMx_Bit

6 Bit

When tm2s.7=1, TM2 PWM resolution is 6 Bit

When tm3s.7=1, TM3 PWM resolution is 6 Bit

7 Bit

When tm2s.7=1, TM2 PWM resolution is 7 Bit

When tm3s.7=1, TM3 PWM resolution is 7 Bit

(ICE does NOT support.)

PFS172 Datasheet(PDF) 86 Page - PADAUK Technology.

PFS172 Datasheet(HTML) 86 Page - PADAUK Technology.

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