PFS172 datasheet(33/92 Pages) PADAUK

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PFS172 Datasheet(PDF) 33 Page - PADAUK Technology.

33 / 92 page

PFS172

8bit MTP MCU with 8-bit ADC

Page 33 of 92

PDK-DS-PFS172-EN_V000-May 8, 2020

5.4.5. System Clock and LVR level

The clock source of system clock comes from EOSC, IHRC and ILRC, the hardware diagram of system clock

in the PFS172 is shown as Fig.3.

Fig.3: Options of System Clock

User can choose different operating system clock depends on its requirement; the selected operating system

clock should be combined with supply voltage and LVR level to make system stable. The LVR level will be

selected during compilation, and the lowest LVR levels can be chosen for different operating frequencies.

Please refer to Section 4.1.

clkmd[7:5]

System

clock

CLK

÷2, ÷4, ÷8,

÷16, ÷32, ÷64

÷1, ÷4, ÷16

÷1, ÷2, ÷4, ÷8

IHRC

EOSC

ILRC

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