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47L16 Datasheet(PDF) 11 Page - Microchip Technology |
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47L16 Datasheet(HTML) 11 Page - Microchip Technology |
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11 / 40 page  2015-2016 Microchip Technology Inc. DS20005371C-page 11 47L04/47C04/47L16/47C16 2.3 SRAM Array The SRAM array is the only directly-accessible memory on the 47XXX. The EEPROM array provides nonvolatile storage to back up the SRAM data. To select the SRAM array, the master device must use the respective 4-bit op code ‘1010’ when transmitting the control byte. 2.3.1 WRITE OPERATION When the SRAM array is selected and the R/W bit in the control byte is set to ‘0’, a write operation is selected and the next two bytes received are interpreted as the array address. The Most Significant address bits are transferred first, followed by the less significant bits, and are shifted directly into the internal Address Pointer. The Address Pointer determines where in the SRAM array the next read or write operation begins. Data bytes are stored into the SRAM array as soon as each byte is received, specifically on the rising edge of SCL during each Acknowledge bit. If a write operation is aborted for any reason, all received data will already be stored in SRAM, except for the last data byte if the rising edge of SCL during the Acknowledge for that byte has not yet been reached. 2.3.1.1 Byte Write After the 47XXX has received the 2-byte array address, responding with an Acknowledge after each address byte, the master device will transmit the data byte to be written into the addressed memory location. The 47XXX acknowledges again, and the master generates a Stop condition (Figure 2-4). The data byte is latched into the SRAM array on the rising edge of SCL during the Acknowledge. After a byte Write command, the internal Address Pointer will point to the address location following the location that was just written. 2.3.1.2 Sequential Write To write multiple data bytes in a single operation, the SRAM write control byte, array address, and the first data byte are transmitted to the 47XXX in the same way as for a byte write. However, instead of generating a Stop condition, the master transmits additional data bytes (Figure 2-5). Upon receipt of each byte, the 47XXX responds with an Acknowledge: during which the data is latched into the SRAM array on the rising edge of SCL, and the Address Pointer is incremented by one. Sequential write operations are limited only by the size of the SRAM array, and if the master should transmit enough bytes to reach the end of the array, the Address Pointer will roll over to 0x000 and continue writing. There is no limit to the number of bytes that can be written in a single command. FIGURE 2-4: SRAM BYTE WRITE Note: If an Auto-Store or Hardware Store is triggered during an SRAM read or write operation, the operation is aborted in order to execute the Store. Note: If an attempt is made to write to a pro- tected portion of the array, the device will not respond with an Acknowledge after the data byte is received, the cur- rent operation will be terminated without incrementing the Address Pointer, and any data transmitted on the SDA line will be ignored until a new operation is begun with a Start condition. Note: If a sequential write crosses into a pro- tected block, the device will not respond with an Acknowledge after the data byte is received, the current operation will be terminated without incrementing the Address Pointer, and any data transmit- ted on the SDA line will be ignored until a new operation is begun with a Start condition. Bus Activity Master SDA Line Bus Activity S T A R T Control Byte Address High Byte Address Low Byte Data S T O P A C K A C K A C K A C K S 101 0 0 A 2 A 1 P 0 X = Don’t Care Y = Don’t Care for 47X04 Data Latched into SRAM XX X X X Y Y |
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