47L16 datasheet(16/40 Pages) MICROCHIP

16 / 40 page

47L04/47C04/47L16/47C16

DS20005371C-page 16

 2015-2016 Microchip Technology Inc.

TABLE 2-5:

PROTECTED ARRAY ADDRESS LOCATIONS

Protected

Range

BP2

BP1

BP0

47X04

47X16

None

——

Upper 1/64

1F8h-1FFh

7E0h-7FFh

Upper 1/32

1F0h-1FFh

7C0h-7FFh

Upper 1/16

1E0h-1FFh

780h-7FFh

Upper 1/8

1C0h-1FFh

700h-7FFh

Upper 1/4

180h-1FFh

600h-7FFh

Upper 1/2

100h-1FFh

400h-7FFh

All Blocks

000h-1FFh

000h-7FFh

STATUS REGISTER

R-0

U-0

R/W

—

BP2

BP1

BP0

ASE

EVENT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

AM:

Array Modified bit

= SRAM array has been modified

= SRAM array has not been modified

bit 6-5

Unimplemented:

Read as ‘0’

bit 4-2

BP<2:0>:

Block Protect bits

000

= Entire array is unprotected

001

= Upper 1/64 of array is write-protected

010

= Upper 1/32 of array is write-protected

011

= Upper 1/16 of array is write-protected

100

= Upper 1/8 of array is write-protected

101

= Upper 1/4 of array is write-protected

110

= Upper 1/2 of array is write-protected

111

= Entire array is write-protected

bit 1

ASE:

Auto-Store Enable bit

= Auto-Store feature is enabled

= Auto-Store feature is disabled

bit 0

EVENT:

Event Detect bit

= An event was detected on the HS pin

= No event was detected on the HS pin

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