Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5

Freescale Semiconductor

15

CPM36

SI SYNC Timing Restriction

Date Added: 5/30/2000

Description: SI’s sync signal may not change exactly on clock edge in the following cases. The

bug affects operation only when the SI is in one of two modes:

fsd = 00, ce = 0, fe = 0, dsc=1

(Sync sampled with falling edge -> Sync should not change on rising edge)

fsd = 00, ce = 1, fe = 1, dsc=1

(Sync sampled with rising edge -> Sync should not change on falling edge).

Workaround: When working in these modes, the sync signal to the SI should be manipulated

such that it does not change on the exact edge of the serial clock. Toggle the sync at least 5ns after

the edge. One way to implement such a workaround is to add a noninverting buffer between the

device that generates the sync signal and the MSC8101 that uses it.

System Number: 3258

Fix Plan: Rev A.

0K40A

CPM38

Heartbeat Error and Carrier Sense Lost Error On Two Frames

Date Added: 5/30/2000

Description: There are rare cases when a heartbeat error and carrier sense lost error are reported

on two frames. The error is reported in the frame in which it occurred, but in those rare cases it is

also reported on an adjacent frame.

Workaround: None

System Number: 1547,1550

Fix Plan: Rev A

0K40A

CPM39

Corruption in AAL0 Cell Payload

Date Added: 5/30/2000

There is a rare case in using the ATM AAL0 transmitter that the AAL0 cell payload may

be corrupted. This can occur in certain internal sequence of events that the user cannot

detect or control.

1. Use the available microcode patch from the web site.

2. When working with AAL0 SAR, place the TCELL_TMP_BASE 64 byte align plus 4.

For example use TCELL_TMB_BASE = 0x2d04 not 0x2d00.

4648a

Rev A

0K40A

Table 2. Silicon Errata (Continued)

Errata

Number

Errata Description

Applies

to Mask