ADRF5043

Data Sheet

Rev. 0 | Page 10 of 12

THEORY OF OPERATION

The ADRF5043 requires a positive supply voltage applied to the

VDD pin and a negative supply voltage applied to the VSS pin.

Bypassing capacitors are recommended on the supply lines to

minimize RF coupling.

All of the RF ports (RFC, RF1 to RF4) are dc-coupled to 0 V,

and no dc blocking is required at the RF ports when the RF line

potential is equal to 0 V. The RF ports are internally matched to

50 Ω. Therefore, external matching networks are not required.

The ADRF5043 integrates a driver to perform logic functions

internally and to provide the user with the advantage of a simplified

CMOS-/LVTTL-compatible control interface. The driver features

four digital control input pins (EN, LS, V1, and V2) that control

the state of the RFx paths (see Table 6).

The logic select input (LS) allows the user to define the control

input logic sequence for the RF path selections. The logic level

applied to the V1 and V2 pins determines which RFx port is in

the insertion loss state while the other three paths are in the

isolation state.

When the EN pin is logic high, all four RFx paths are in

isolation state regardless of the logic state of LS, V1, V2. RFx

ports are terminated to internal 50 Ω resistors, and RFC

becomes reflective.

The insertion loss path conducts the RF signal between the

selected RF throw port and the RF common port. The switch

design is bidirectional with equal power handling capabilities.

The RF input signal can be applied to the RFC port or the

selected RF throw port. The isolation paths provide high loss

between the insertion loss path and the unselected RF throw

ports that are terminated to internal 50 Ω resistors.

The ideal power-up sequence is as follows:

1. Connect GND to ground.

2. Power up VDD and VSS. Powering up VSS after VDD

avoids current transients on VDD during ramp up.

3. Apply a control voltage to the digital control inputs (EN,

LS, V1, and V2). Applying a control voltage to the digital

control inputs before the VDD supply can inadvertently

forward bias and damage the internal ESD protection

structures. Use a series 1 kΩ resistor to limit the current

flowing into the control pin in such cases. If the control

pins are not driven to a valid logic state (that is, controller

output is in high impedance state) after VDD is powered

up, it is recommended to use a pull-up or pull-down

resistor.

4. Apply an RF input signal.

The ideal power-down sequence is the reverse order of the

power-up sequence.

Table 6. Control Voltage Truth Table

Digital Control Inputs

RFx Paths

EN

LS

V1

V2

RFC to RF1

RFC to RF2

RFC to RF3

RFC to RF4

Low

Low

Low

Low

Insertion loss (on)

Isolation (off)

Isolation (off)

Isolation (off)

Low

Low

High

Low

Isolation (off)

Insertion loss (on)

Isolation (off)

Isolation (off)

Low

Low

Low

High

Isolation (off)

Isolation (off)

Insertion loss (on)

Isolation (off)

Low

Low

High

High

Isolation (off)

Isolation (off)

Isolation (off)

Insertion loss (on)

Low

High

Low

Low

Isolation (off)

Isolation (off)

Isolation (off)

Insertion loss (on)

Low

High

High

Low

Isolation (off)

Isolation (off)

Insertion loss (on)

Isolation (off)

Low

High

Low

High

Isolation (off)

Insertion loss (on)

Isolation (off)

Isolation (off)

Low

High

High

High

Insertion loss (on)

Isolation (off)

Isolation (off)

Isolation (off)

High

Low or high

Low or high

Low or high

Isolation (off)

Isolation (off)

Isolation (off)

Isolation (off)