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ADRF5043BCCZN-R7 Datasheet(PDF) 11 Page - Analog Devices

Part # ADRF5043BCCZN-R7
Description  Nonreflective, 9 kHz to 44 GHz Silicon SP4T Switch
PDF  12 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADRF5043BCCZN-R7 Datasheet(HTML) 11 Page - Analog Devices

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Data Sheet
ADRF5043
Rev. 0 | Page 11 of 12
APPLICATION INFORMATION
EVALUATION BOARD
All measurements in this data sheet are measured on the
ADRF5043-EVALZ evaluation board. Figure 24 shows the
simplified application circuit for ADRF5043-EVALZ evaluation
board. See the ADRF5043-EVALZ user guide for more
information on using the evaluation board.
The design of the ADRF5043-EVALZ board serves as a layout
recommendation. The Gerber files of the ADRF5043-EVALZ
evaluation board are available at www.analog.com/EVAL-
ADRF5043.
The ADRF5043-EVALZ is a 4-layer evaluation board. The outer
copper (Cu) layers are 0.5 oz (0.7 mil) plated to 1.5 oz (2.2 mil)
and are separated by dielectric materials. Figure 22 shows the
cross sectional view of the evaluation board stackup.
0.5oz Cu (0.7mil)
RO4003
0.5oz Cu (0.7mil)
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
W = 14mil
G = 7mil
T = 2.2mil
H = 8mil
1.5oz Cu (2.2mil)
1.5oz Cu (2.2mil)
Figure 22. Evaluation Board Cross Sectional View
All RF traces are routed on the top copper layer, whereas the
inner and bottom layers are grounded planes that provide a
solid ground for the RF transmission lines. The top dielectric
material is 8 mil Rogers RO4003, offering optimal high frequency
performance. The middle and bottom dielectric materials
provide mechanical strength. The total board thickness is
62 mil, which allows 2.4 mm RF launchers to be connected at
the board edges.
The RF transmission lines were designed using a coplanar
waveguide (CPWG) model, with a trace width of 14 mil and a
ground clearance of 7 mil to have a characteristic impedance of
50 Ω. The RF transmission lines are tapered at the RFC or RFx
pin transition, as shown in Figure 23. For optimal RF and
thermal grounding, arrange as many plated through vias as
possible around the transmission lines and under the exposed
pad of the package.
Figure 23. RF Trasmission Lines
V1
EN
CMOS/LVTTL
CMOS/LVTTL
CMOS/LVTTL
–3.3V
3.3V
100pF
100pF
RFC
RF4
RF1
VSS
VDD
V2
RF2
RF3
1
2
3
4
5
6
LS
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ADRF5043
50Ω
50Ω
50Ω
50Ω
50Ω
Figure 24. Application Circuit



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