iCE40 LP/HX Family

Data Sheet

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FPGA-DS-02029-3.5

3

5.

Pinout Information .....................................................................................................................................................38

5.1.

Signal Descriptions ............................................................................................................................................38

5.1.1.

General Purpose ...........................................................................................................................................38

5.1.2.

PLL and Global Functions (Used as user-programmable I/O pins when not used for PLL or clock pins)......38

5.1.3.

Programming and Configuration ..................................................................................................................38

5.2.

Pin Information Summary .................................................................................................................................40

5.3.

iCE40 LP/HX Part Number Description..............................................................................................................43

5.3.1.

Ultra Low Power (LP) Devices .......................................................................................................................43

5.3.2.

High Performance (HX) Devices ....................................................................................................................43

5.4.

Ordering Information ........................................................................................................................................44

5.5.

Ordering Part Numbers.....................................................................................................................................44

5.5.1.

Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging ...............................................44

5.5.2.

High-Performance Industrial Grade Devices, Halogen Free (RoHS) Packaging.............................................45

Supplemental Information .................................................................................................................................................46

Technical Support ...............................................................................................................................................................47

Revision History ..................................................................................................................................................................48

Figures

Figure 3.1. iCE40LP/HX1K Device, Top View.........................................................................................................................8

Figure 3.2. PLB Block Diagram ..............................................................................................................................................9

Figure 3.3. PLL Diagram ......................................................................................................................................................11

Figure 3.4. sysMEM Memory Primitives.............................................................................................................................13

Figure 3.5. I/O Bank and Programmable I/O Cell ...............................................................................................................15

Figure 3.6. iCE I/O Register Block Diagram .........................................................................................................................16

Figure 4.1. LVDS25E Using External Resistors.....................................................................................................................26

Figure 4.2. subLVDSE DC Conditions...................................................................................................................................27

Figure 4.3. Output Test Load, LVCMOS Standards .............................................................................................................37

Figure 5.1. Low Power (LP) Devices ....................................................................................................................................43

Figure 5.2. High Performance (HX) Devices........................................................................................................................43

Figure 5.3. High Performance (HX) Devices........................................................................................................................44