iCE40 LP/HX Family

Data Sheet

© 2011-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-DS-02029-3.5

9

document. The sysMEM EBRs are large 4 kbit, dedicated fast memory blocks. These blocks can be configured as RAM,

ROM or FIFO.

The iCE40 LP/HX architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks. The PLLs have

multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase relationships of the

clocks.

Every device in the family has a SPI port that supports programming and configuration of the device. The iCE40 LP/HX

includes on-chip, Nonvolatile Configuration Memory (NVCM).

3.1.1. PLB Blocks

The core of the iCE40 LP/HX device consists of Programmable Logic Blocks (PLB) which can be programmed to perform

contains one LUT and one register.

Figure 3.2. PLB Block Diagram

Logic Cells



A four-input Look-Up Table (LUT) builds any combinational logic function, of any complexity, requiring up to four

inputs. Similarly, the LUT4 element behaves as a 16 x 1 Read-Only Memory (ROM). Combine and cascade multiple

LUT4s to create wider logic functions.



A D-style Flip-Flop (DFF), with an optional clock-enable and reset control input, builds sequential logic functions.

Each DFF also connects to a global reset signal that is automatically asserted immediately following device

configuration.



Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters,

comparators, binary counters and some wide, cascaded logic functions.

Table 3.1 lists the logic cell signals.