iCE40 LP/HX Family

Data Sheet

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2

FPGA-DS-02029-3.5

Contents

Acronyms in This Document .................................................................................................................................................5

1.

General Description ......................................................................................................................................................6

1.1.

Features...............................................................................................................................................................6

2.

Product Family ..............................................................................................................................................................7

3.

Architecture ..................................................................................................................................................................8

3.1.

Architecture Overview ........................................................................................................................................8

3.1.1.

PLB Blocks .......................................................................................................................................................9

3.1.2.

Routing..........................................................................................................................................................10

3.1.3.

Clock/Control Distribution Network .............................................................................................................10

3.1.4.

sysCLOCK Phase Locked Loops (PLLs) ...........................................................................................................11

3.1.5.

sysMEM Embedded Block RAM Memory .....................................................................................................12

3.1.6.

sysI/O ............................................................................................................................................................14

3.1.7.

sysI/O Buffer .................................................................................................................................................17

3.1.8.

Non-Volatile Configuration Memory ............................................................................................................18

3.1.9.

Power On Reset ............................................................................................................................................18

3.2.

Programming and Configuration.......................................................................................................................18

3.2.1.

Power Saving Options ...................................................................................................................................18

4.

DC and Switching Characteristics................................................................................................................................19

4.1.

Absolute Maximum Ratings ..............................................................................................................................19

4.2.

Recommended Operating Conditions ...............................................................................................................19

4.3.

Power Supply Ramp Rates.................................................................................................................................20

4.4.

Power-On-Reset Voltage Levels ........................................................................................................................20

4.5.

ESD Performance...............................................................................................................................................20

4.6.

DC Electrical Characteristics ..............................................................................................................................21

4.7.

Static Supply Current – LP Devices ....................................................................................................................21

4.8.

Static Supply Current – HX Devices ...................................................................................................................22

4.9.

Programming NVCM Supply Current – LP Devices............................................................................................22

4.10.

Programming NVCM Supply Current – HX Devices ...........................................................................................23

4.11.

Peak Startup Supply Current – LP Devices ........................................................................................................23

4.12.

Peak Startup Supply Current – HX Devices........................................................................................................24

4.13.

sysI/O Recommended Operating Conditions ....................................................................................................24

4.14.

sysI/O Single-Ended DC Electrical Characteristics .............................................................................................24

4.15.

sysI/O Differential Electrical Characteristics .....................................................................................................25

4.15.1.

LVDS25......................................................................................................................................................25

4.15.2.

subLVDS ....................................................................................................................................................25

4.16.

LVDS25E Emulation ...........................................................................................................................................26

4.17.

SubLVDS Emulation ...........................................................................................................................................27

4.18.

Typical Building Block Function Performance – LP Devices* ............................................................................28

4.18.1.

Pin-to-Pin Performance (LVCMOS25) – LP Devices ..................................................................................28

4.18.2.

Register-to-Register Performance – LP Devices .......................................................................................28

4.19.

Typical Building Block Function Performance – HX Devices*............................................................................28

4.19.1.

Pin-to-Pin Performance (LVCMOS25) – HX Devices .................................................................................28

4.19.2.

Register-to-Register Performance – HX Devices ......................................................................................29

4.20.

Derating Logic Timing........................................................................................................................................29

4.21.

Maximum sysI/O Buffer Performance...............................................................................................................29

4.22.

Timing Adders ...................................................................................................................................................30

4.23.

External Switching Characteristics – LP Devices................................................................................................31

4.24.

External Switching Characteristics – HX Devices...............................................................................................33

4.25.

sysClock PLL Timing ...........................................................................................................................................34

4.26.

SPI Master or NVCM Configuration Time..........................................................................................................35

4.27.

sysCONFIG Port Timing Specifications...............................................................................................................36

4.28.

Switching Test Conditions .................................................................................................................................37