A6986H datasheet(50/71 Pages) STMICROELECTRONICS

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Figure 51. Master driving capability to synchronize the A6986H

7.6

Design of the power components

7.6.1

Input capacitor selection

The input capacitor voltage rating must be higher than the maximum input operating voltage of the application.

During the switching activity a pulsed current flows into the input capacitor and so its RMS current capability must

be selected accordingly with the application conditions. Internal losses of the input filter depends on the ESR

value so usually low ESR capacitors (like multilayer ceramic capacitors) have higher RMS current capability. On

the other hand, given the RMS current value, lower ESR input filter has lower losses and so contributes to higher

conversion efficiency.

The maximum RMS input current flowing through the capacitor can be calculated as:

IRMS=IOUT⋅ (1−Dη)⋅Dη

(43)

Where IOUT is the maximum DC output current, D is the duty cycles, ƞ is the efficiency. This function has a

maximum at D = 0.5 and, considering h = 1, it is equal to IOUT/2.

In a specific application the range of possible duty cycles has to be considered in order to find out the maximum

RMS input current. The maximum and minimum duty cycles can be calculated as:

DMAX=

VOUT+ΔVLOWSIDE

VINMIN+ΔVLOWSIDE−VINMIN+ΔVHIGHSIDE

(44)

DMIN=

VOUT+ΔVLOWSIDE

VINMAX+ΔVLOWSIDE−VINMIN+ΔVHIGHSIDE

(45)

Where DVHIGH_SIDE and DVLOW_SIDE are the voltage drops across the embedded switches. The peak-to-peak

voltage across the input filter can be calculated as follows:

CIN= IOUT

VPP⋅fSW⋅(1−Dη)⋅Dη+ESR⋅(IOUT+ΔIL)

(46)

In case of negligible ESR (MLCC capacitor) the equation of CIN as a function of the target VPP can be written as

follows:

CIN= IOUT

VPP⋅fSW⋅(1−Dη)⋅Dη

(47)

Considering ƞ=1 this function has its maximum in D = 0.5:

CINMIN= IOUT

4⋅VPPMAX⋅fSW

(48)

Typically CIN is dimensioned to keep the maximum peak-peak voltage across the input filter in the order of 5%

VIN_MAX.

A6986H

Design of the power components

DS12861 - Rev 3

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