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STM32L552CCT3PTR Datasheet(PDF) 57 Page - STMicroelectronics |
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STM32L552CCT3PTR Datasheet(HTML) 57 Page - STMicroelectronics |
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57 / 340 page ![]() DS12737 Rev 6 57/340 STM32L552xx Functional overview 78 3.17 Interrupts and events 3.17.1 Nested vectored interrupt controller (NVIC) The devices embed a nested vectored interrupt controller which is able to manage 8 priority levels, and to handle up to 109 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-M33. The NVIC benefits are the following: • Closely coupled NVIC gives low latency interrupt processing • Interrupt entry vector table address passed directly to the core • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead • TrustZone support. The NVIC registers are banked across secure and non-secure states The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.17.2 Extended interrupt/event controller (EXTI) The Extended interrupts and event controller (EXTI) manages the individual CPU and system wakeup through configurable and direct event inputs. It provides wakeup requests to the power control, and generates an interrupt request to the CPU NVIC and events to the CPU event input. For the CPU an additional Event Generation block (EVG) is needed to generate the CPU event signal. The EXTI wakeup requests allow the system to be woken up from Stop modes. The interrupt request and event request generation can also be used in RUN modes. The EXTI also includes the EXTI mux IOport selection. The EXTI main features are the following: The EXTI main features are the following: • 43 input events supported • All event inputs allow to wake up the system. • Events which do not have an associated wakeup flag in the peripheral, have a flag in the EXTI and generate an interrupt to the CPU from the EXTI. |
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