STM32L552CCT3PTR datasheet(75/340 Pages) STMICROELECTRONICS

75 / 340 page

DS12737 Rev 6

75/340

STM32L552xx

Functional overview

3.35

Low-power universal asynchronous receiver transmitter

(LPUART)

The devices embed one low-power UART. The LPUART supports asynchronous serial

communication with minimum power consumption. It supports half-duplex single-wire

communication and modem operations (CTS/RTS). It allows multiprocessor

communication.

The LPUART has a clock domain independent from the CPU clock, and can wakeup the

system from Stop mode using baudrates up to 220 Kbaud. The wake up events from Stop

mode are programmable and can be:

•

Start bit detection

•

Any received data frame

•

A specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600

baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while

having an extremely low energy consumption. Higher speed clock can be used to reach

higher baudrates.

The LPUART interface can be served by the DMA controller.

3.36

Serial peripheral interface (SPI)

Three SPI interfaces allow communication up to slave modes, in half-duplex, full-duplex and

simplex modes. The 3-bit prescaler gives eight master mode frequencies and the frame size

is configurable from 4 bits to 16 bits. The SPI interfaces support NSS pulse mode, TI mode

and hardware CRC calculation.

All SPI interfaces can be served by the DMA controller.

3.37

Serial audio interfaces (SAI)

The devices embed two SAI. Refer to Table 19: SAI implementation for the features

implementation. The SAI bus interface handles communications between the

microcontroller and the serial audio protocol.

The SAI peripheral supports:

•

Two independent audio sub-blocks which can be transmitters or receivers with their

respective FIFO.

•

8-word integrated FIFOs for each audio sub-block.

•

Synchronous or asynchronous mode between the audio sub-blocks.

•

Master or slave configuration independent for both audio sub-blocks.

•

Clock generator for each audio block to target independent audio frequency sampling

when both audio sub-blocks are configured in master mode.

•

Data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit.

•

Peripheral with large configurability and flexibility allowing to target as example the

following audio protocol: I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF

out.

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