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STM32WB55CCV6ATR Datasheet(PDF) 43 Page - STMicroelectronics |
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STM32WB55CCV6ATR Datasheet(HTML) 43 Page - STMicroelectronics |
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43 / 193 page  DS11929 Rev 10 43/193 STM32WB55xx STM32WB35xx Functional overview 57 Figure 9. Clock tree 1. The LCD is not available on STM32WB35xx devices. 3.11 General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be achieved thanks to their mapping on the AHB2 bus. MS45402V7 SMPS clock source control LSI1 RCC 32 kHz LSI2 RCC 32 kHz LSE OSC 32.768 kHz LSCO LSI to IWDG HSE OSC 32 MHz HSE CSS OSC_IN OSC_OUT HSI16 RC 16 MHz MSI RC 100 kHz - 48 MHz MCO /1 - 16 /32 HSI48 RC 48 MHz LSE CSS /32 PLL /P /R /Q PLLSAI1 /P /R /Q /M SYSCLK MSI MSI HSI16 HSI16 HSE HSE PLLRCLK PLLRCLK RC48 LSE LSI2 LSI1 SYS clock source control SYSCLK MSI HSI16 HCLK1 HCLK2 HCLK4 APB1 PPRE1 /1,2,4,8,16 to CPU1, AHB1, AHB2, AHB3, and SRAM1 to CPU1 FCLK /8 to CPU1 system timer APB2 PPRE2 /1,2,4,8,16 PCLK1 PCLK2 to CPU2 to CPU2 FCLK /8 to CPU2 system timer to AHB4, Flash memory, SRAM2 to APB1 TIMx to APB2 TIMx to USART1 to LPTIMx to LPUART1 to SAI1 to ADC1 to RTC and LCD (1) x1 or x2 x1 or x2 to I2Cx PCLKn SYSCLK HSI16 HSI16 PCLKn LSI LSE HSI16 SAI1_EXTCLK PLLSAI1PCLK PLLPCLK SYSCLK PCLKn LSE to 802.15.4 wakeup HCLK5 HSI16 HSE to AHB5 to APB3 to APB2 to APB1 to RF PLLSAI1RCLK SYSCLK to USB HSI48 MSI to RNG PLLQCLK PLLRCLK PLLSAI1QCLK OSC32_IN OSC32_OUT LSI LSE LSE MSI HSI16 HSE SMPSDIV /1,2,3,4,6,8,12 to SMPS /2 xN xN to BLE wakeup CPU1 HPRE /1,2,...,512 AHB4 SHDHPRE /1,2,...,512 CPU2 C2HPRE 1,2,...,512 HSI16 HSEPRE/1,2 /3 LSI LSE /2 |
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