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DP83241 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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DP83241 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
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6 / 20 page ![]() 30 Pin Descriptions (Continued) Symbol Pin IO Description No VCO RST 11 I VCO Reset TTL compatible input used to reset the internal VCO on system power up This input stops the VCO from oscillating when at a logic HI level thereby reinitializing each of the gates in the ring oscillator TXCa 3 O Transmit Clock 100K ECL compatible differential outputs for use at 125 MHz as the fiber medium Transmit Clock (TXC) source for the PLAYER device TXCb 2 TBCa 27 O Transmit Byte Clock 100K ECL compatible differential outputs for use at 125 MHz as a load strobe or transmit byte clock by the PLAYER device to convert byte wide data to serial format for TBCb 26 fiber medium transmission These outputs are positioned to transition on the falling edge of the TXC a clock output to provide the maximum setup and hold margin They are also phase coherent with the TTL LBC1 output but the phase transition occurs approximately 10 ns earlier LBC1 thru 5 25 24 O Local Byte Clocks TTL compatible local byte clock outputs which are phase locked to crystal oscillator reference signals These outputs have a 50% duty cycle waveform at 125 MHz The 23 22 21 PHASE SEL input determines whether the five phase outputs are phase offset by 8 ns or 16 ns LSC 20 O Local Symbol Clock TTL compatible 25 MHz output for driving the BMAC device This output’s negative phase transition is aligned with the LBC1 output transitions and has a 40% HI and 60% LOW duty cycle PHASE SEL 19 I Phase Select TTL compatible input used to select eithera8nsor16ns phase offset between the 5 local byte clocks The LBC’s are phase offset 8 ns apart when PHASE SEL is at a logic LOW level and 16 ns apart when at a logic HI level 6 |
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