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XIO2000AI Datasheet(PDF) 128 Page - Texas Instruments

Part # XIO2000AI
Description  XIO2000A/XIO2000AI PCI Express to PCI Bus Translation Bridge
PDF  165 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

XIO2000AI Datasheet(HTML) 128 Page - Texas Instruments

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Memory-Mapped TI Proprietary Register Space
119
April 2007 Revised October 2008
SCPS155C
6.2
Revision ID Register
The revision ID register identifies the revision of the TI proprietary layout for this device control map. The value
00h identifies the revision as the initial layout.
Device control memory window register offset:
01h
Register type:
Read-only
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
6.3
Upstream Isochrony Capabilities Register
The upstream isochronous capabilities register provides software information regarding the capabilities
supported by this bridge. See Table 6−2 for a complete description of the register contents.
Device control memory window register offset:
02h
Register type:
Read-only
Default value:
0004h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Table 6−2. Upstream Isochronous Capabilities Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:4
RSVD
R
Reserved. Returns 000h when read.
3:0
ISOC_WINDOW_COUNT
R
Isochronous window count. This 4-bit field indicates the number of isochronous address
windows supported. The value 0100b indicates that 4 separate windows are supported
by the bridge.



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